Title
A 5-to-25Gb/s 1.6-to-3.8mW/(Gb/s) reconfigurable transceiver in 45nm CMOS
Abstract
A reconfigurable transceiver capable of adapting its signaling mode to the I/O channel is implemented in 45nm CMOS. When configured for single-ended 2/3/4-PAM, it enables 5-to-25Gb/s signaling over on-package interconnect while dissipating 1.6-to-2.6mW/(Gb/s). Over a backplane channel, a differential source series-terminated signaling configuration with TX pre-emphasis and 1-tap DFE allows 10Gb/s signaling with 3.8mW/(Gb/s) power efficiency.
Year
DOI
Venue
2010
10.1109/ISSCC.2010.5433826
Solid-State Circuits Conference Digest of Technical Papers
Keywords
Field
DocType
CMOS integrated circuits,integrated circuit interconnections,integrated circuit packaging,pulse amplitude modulation,transceivers,CMOS,I/O channel,TX pre-emphasis,backplane channel,bit rate 5 Gbit/s to 25 Gbit/s,differential source series-terminated signaling configuration,on-package interconnect,power 1.6 mW to 3.8 mW,reconfigurable transceiver,signaling mode,single-ended 2/3/4-PAM,size 45 nm
Electrical efficiency,Transceiver,Equalization (audio),Backplane,Computer science,Communication channel,CMOS,Electronic engineering,Pulse-amplitude modulation,Scalability
Conference
ISSN
ISBN
Citations 
0193-6530
978-1-4244-6033-5
2
PageRank 
References 
Authors
0.81
0
6
Name
Order
Citations
PageRank
Ganesh Balamurugan114420.77
Frank O'Mahony210220.28
Mozhgan Mansuri315425.15
James E. Jaussi412526.64
Joseph T. Kennedy510617.78
Bryan Casper614725.64