Name
Abstract | ||
|---|---|---|
Two methods to apply tests to detect delay faults in standard scan designs are used. One is called launch off capture and the other is called launch off shift. Launch off shift test method has the advantage that it provides higher fault coverage at reduced test generation time and test pattern counts. However a concern expressed often in the literature is the potential over testing or yield loss caused by the fact that launch off shift operates the circuit under test in non-functional manner. In this paper we present data, for the first time, which points to another potential problem with launch off shift tests. The data presented for ISCAS-89 benchmark circuits shows that a considerable numbers of functionally detectable transition delay faults are not detected by the normally used launch off shift tests that use a single fault activation cycle. Functionally detectable faults that escape tests could cause circuit malfunction in normal operation. Thus launch off shift tests when used in manufacturing test may result in test escapes. We also present data that shows that if launch off shift tests with multiple fault activation cycles are used essentially all functionally detectable faults can be detected. |
Year | DOI | Venue |
|---|---|---|
2007 | 10.1109/ASPDAC.2007.358090 | ASP-DAC |
Keywords | Field | DocType |
functionally detectable fault,detect delay faults test,test generation time,transition delay faults,test escapes,integrated circuit testing,shift test,test pattern counts,test escape,iscas-89 benchmark circuits,escape test,delay faults,shift test method,automatic test pattern generation,launch off capture test,test pattern count,fault diagnosis,scan designs,present data,single fault activation cycle,shift tests,functionally detectable transition delay,reduced test generation time,fault coverage,launch off shift test,delay fault,circuit under test,test methods,shift operator,normal operator | Automatic test pattern generation,Test method,Fault coverage,Computer science,Electronic engineering,Real-time computing,Electronic circuit,Circuit under test | Conference |
ISSN | ISBN | Citations |
2153-6961 | 1-4244-0630-7 | 3 |
PageRank | References | Authors |
0.41 | 10 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Zhuo Zhang | 1 | 70 | 3.49 |
| Sudhakar M. Reddy | 2 | 5747 | 699.51 |
| Irith Pomeranz | 3 | 3829 | 336.84 |