Paper Info
Title
SIFAR: Static Test Compaction for Synchronous Sequential Circuits Based on Single Fault Restoration
Abstract
We propose a new approach for implementing static compaction procedures for synchronous sequential circuits. The procedures we consider belong to the class of procedures that generate the compacted test sequence through restoration of segments (or subsequences) of a given test sequence T. Under the proposed approach, each restored segment detects a single target fault chosen from the faults detected by T at one time unit. A novel parallel pattern simulator is developed for this purpose. Experimental results for benchmark circuits are included.
Year
DOI
Venue
2000
10.1109/VTEST.2000.843847
VTS
Keywords
Field
DocType
static test compaction,novel parallel pattern simulator,single target fault,synchronous sequential circuit,new approach,static compaction procedure,synchronous sequential,single fault restoration,test sequence t.,benchmark circuit,compacted test sequence,compaction,engines,sequential circuits,fault detection,automatic test pattern generation,sequential analysis,fault coverage
Automatic test pattern generation,Sequential logic,Fault coverage,Computer science,Logic testing,Test sequence,Algorithm,Real-time computing,Electronic engineering,Unit of time,Static test compaction,Electronic circuit
Conference
ISBN
Citations 
PageRank 
0-7695-0613-5
16
0.67
References 
Authors
14
4
Name
Order
Citations
PageRank
Xijiang Lin168742.03
Wu-tung Cheng21350121.45
Irith Pomeranz33829336.84
Sudhakar M. Reddy45747699.51