Name
Title | ||
|---|---|---|
Coordinated transformations for high-level synthesis of high performance microprocessor blocks |
Abstract | ||
|---|---|---|
High performance microprocessor designs are partially characterized by functional blocks consisting of a large number of operations that are packed into very few cycles (often single-cycle) with little or no resource constraints but tight bounds on the cycle time. Extreme parallelization, conditional and speculative execution of operations is essential to meet the processor performance goals. However, this is a tedious task for which classical high-level synthesis (HLS) formulations are inadequate and thus rarely used. In this paper, we present a new methodology for application of HLS targeted to such microprocessor functional blocks that can potentially speed up the design space exploration for microprocessor designs. Our methodology consists of a coordinated set of source-level and fine-grain parallelizing compiler transformations that targets these behavioral descriptions, specifically loop constructs in them and enables efficient chaining of operations and high-level synthesis of the functional blocks. As a case study in understanding the complexity and challenges in the use of HLS, we walk the reader through the detailed design of an instruction length decoder drawn from the Pentium®-family of processors. The chief contribution of this paper is formulation of a domain-specific methodology for application of high-level synthesis techniques to a domain that rarely, if ever, finds use for it. |
Year | DOI | Venue |
|---|---|---|
2002 | 10.1145/513918.514140 | DAC |
Keywords | Field | DocType |
high-level synthesis,high performance microprocessor design,new methodology,high-level synthesis technique,design space exploration,microprocessor design,coordinated transformation,classical high-level synthesis,microprocessor functional block,functional block,high performance microprocessor block,domain-specific methodology,space exploration,design automation,cycle time,hardware description languages,high performance computing,coordinate transformation,high level synthesis,design,embedded computing,speculative execution,integrated circuit design | Computer science,Real-time computing,Electronic engineering,Hardware description language,Computer architecture,Chaining,Speculative execution,Parallel computing,Microprocessor,High-level synthesis,Compiler,Pentium,Design space exploration | Conference |
ISBN | Citations | PageRank |
1-58113-461-4 | 4 | 0.43 |
References | Authors | |
10 | 8 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Sumit Gupta | 1 | 221 | 13.28 |
| Nick Savoiu | 2 | 109 | 10.21 |
| Nikil Dutt | 3 | 4960 | 421.49 |
| Rajesh Gupta | 4 | 4 | 0.43 |
| Alex Nicolau | 5 | 858 | 56.64 |
| Timothy Kam | 6 | 4 | 0.43 |
| Michael Kishinevsky | 7 | 814 | 67.81 |
| Shai Rotem | 8 | 102 | 7.33 |