Name
Title | ||
|---|---|---|
Asynchronous Implementation Of The Add Compare Select Processor For Communication Systems |
Year | DOI | Venue |
|---|---|---|
1994 | 10.1109/ISCAS.1994.409156 | ISCAS |
Keywords | Field | DocType |
viterbi decoding,communication system,adders | Cmos logic circuits,Asynchronous communication,Bottleneck,Computer architecture,Adder,Computer science,Communications system,Electronic engineering,CMOS,Viterbi decoder,Viterbi algorithm | Conference |
Citations | PageRank | References |
0 | 0.34 | 0 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Aria Eshraghi | 1 | 13 | 3.62 |
| Terri S. Fiez | 2 | 167 | 47.25 |
| Thomas R. Fischer | 3 | 185 | 39.19 |