Name
Abstract | ||
|---|---|---|
Lazy hardware transactional memory (HTM) al-lows better utilization of available concurrency in transactional workloads than eager HTM, but poses challenges at commit time due to the requirement of en-masse publication of speculative updates to global system state. Early conflictdetection can be employed in lazy HTM designs to allow non-conflicting transactions to commit in parallel. Though this has the potential to improve performance, it has not been utilized effectively so far. Prior work in the area burdens common-case transactional execution severely to avoid some relatively uncommon correctness concerns. In this work we investigate this problem and introduce a novel design, p-TM, which eliminates this problem. p-TM uses modest extensions to existing directory-based cache coherence protocols to keep a record of conflicting cache lines as a transaction executes. This information allows a consistent cache state to be maintained when transactions commit or abort. We observe that contention is typically seen only on a small fraction of shared data accessed by coarse-grained transactions. In p-TM earlyconflict detection mechanisms imply additional work only when such contention actually exists. Thus, the design is able to avoid expensive core-to-core and core-to-directory communication for a large part of transactionally accessed data. Our evalutation shows major performance gains when compared to other HTM designs in this class and competitive performance when compared to more complex lazy commit schemes. |
Year | DOI | Venue |
|---|---|---|
2011 | 10.1109/HPCA.2012.6168951 | HPCA '12 Proceedings of the 2012 IEEE 18th International Symposium on High-Performance Computer Architecture |
Keywords | DocType | ISSN |
scalable lazy hardware transactional,pessimistic invalidation,consistent cache state,directory-based cache coherence protocol,common-case transactional execution,lazy conflict resolution design,design choice,conflicting cache line,lazy htm,eager htm,lazy htm design,lazy hardware transactional memory,possible conflict,early conflict detection,competitive performance,major performance gain,lazy design,htm design,additional work,early conflict,common-case execution,transactional memory,conflict resolution | Conference | 1089-795X |
ISBN | Citations | PageRank |
978-1-4577-1794-9 | 8 | 0.43 |
References | Authors | |
10 | 5 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Anurag Negi | 1 | 49 | 5.08 |
| Per Stenström | 2 | 3048 | 234.09 |
| Rubén Titos-Gil | 3 | 79 | 10.41 |
| M. E. Acacio | 4 | 419 | 41.45 |
| Jose M. Garcia | 5 | 145 | 13.30 |