Name
Abstract | ||
|---|---|---|
This paper presents a 12-bit 50-MS/s successive-approximation (SAR) analog-to digital (ADC) with high power efficiency. By splitting MSB capacitors an efficient step switching scheme is proposed to reduce average switching energy of the capacitive DAC by 93.75% as compared to conventional method. The settling time is partially optimized in half of the conversion steps. Prototype is designed in a 65-nm CMOS technology and the power consumption is 2.0mW under a 1.2-V power supply. |
Year | DOI | Venue |
|---|---|---|
2013 | 10.1109/MWSCAS.2013.6674858 | Circuits and Systems |
Keywords | Field | DocType |
step switching,cmos integrated circuits,power efficient sar adc,power consumption,power 2.0 mw,analogue-digital conversion,voltage 1.2 v,size 65 nm,successive-approximation,low-power electronics,capacitors,msb capacitors,capacitive dac,cmos technology,optimized settling,word length 12 bit,digital-analogue conversion,analog-to digital,low power electronics | Settling,Electrical efficiency,Capacitor,Settling time,Computer science,Electronic engineering,CMOS,Capacitive sensing,Successive approximation ADC,Electrical engineering,Low-power electronics | Conference |
Volume | Issue | ISSN |
null | null | 1548-3746 |
Citations | PageRank | References |
1 | 0.39 | 4 |
Authors | ||
6 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Weiru Gu | 1 | 7 | 1.19 |
| Hao Zhou | 2 | 2 | 3.44 |
| Tao Lin | 3 | 1 | 0.39 |
| Zhenyu Wang | 4 | 41 | 29.53 |
| Fan Ye | 5 | 34 | 21.14 |
| Junyan Ren | 6 | 154 | 41.40 |