Paper Info
Title
On the Mapping of Incremental Redundancy into a Physical Layer ASIC
Abstract
Incremental Redundancy (IR) was introduced in GSM/EDGE and later adopted in Evolved EDGE in order to keep the throughput at an acceptable level. Legacy 2G networks with their ubiquitous coverage are apt to provide a fallback solution for the latest LTE networks. On the other hand, they provide a reliable data link for emerging M2M or IoT applications. IR data processing and controlling is specified in several layers of the GSM/EDGE protocol stack. In many state-of-the-art designs this leads to decentralized data processing, and thus to costly data movements between memories and hardware accelerators. This is prohibitive for emerging M2M designs, which demand lowest possible hardware resources. In this work, IR is implemented as part of a dedicated hardware baseband signal processing unit in order to unburden higher layer processing units from IR, reduce area, power consumption, and costs. The open source baseband framework MatPHY is extended for packet switched operation to facilitate the development of efficient IR hardware architectures. With the design parameters obtained from performance evaluations computed with MatPHY an IR architecture in a 130 nm CMOS technology is presented. Said architecture proves the suitability of an ASIC IR unit instead of a software solution distributed over various layers and components.
Year
DOI
Venue
2015
10.1007/s11265-014-0949-1
Journal of Signal Processing Systems
Keywords
Field
DocType
GSM,EDGE,Evolved EDGE,Incremental Redundancy,MatPHY,M2M,IoT
Baseband,GSM,Computer science,Parallel computing,Real-time computing,Application-specific integrated circuit,Physical layer,Software,Throughput,Protocol stack,Data link,Embedded system
Journal
Volume
Issue
ISSN
78
3
1939-8018
Citations 
PageRank 
References 
0
0.34
5
Authors
4
Name
Order
Citations
PageRank
Benjamin Weber162.26
Harald Kroll2175.08
Christian Benkeser3647.86
Qiuting Huang4399145.90