Paper Info
Title
Modeling framework for cross-point resistive memory design emphasizing reliability and variability issues
Abstract
Resistive RAM (ReRAM) cross-point memory technology is one of the most promising candidates for future memory designs as it offers small cell area, fast write latency, and excellent scalability. However, it also suffers from more severe reliability issues than other Non-volatile Memory (NVM) technologies. Due to the lack of access device, ReRAM cells cannot be turned off completely and thus write disturbance problem and hard errors can affect the memory array reliability. Moreover, ReRAM cell suffers from temporal variation caused by its stochastic nature, which results in the resistance change. In this paper, pseudo-hard error caused by temporal variation is defined for the first time as a unique type of error in ReRAM cross-point structure. A comprehensive model is proposed to numerically evaluate all kinds of reliability and variability issues including voltage drop, read/write disturbance, spatial/temporal variations, and hard errors. Detailed analysis are presented, and mitigation solutions including dual-port write and test-and-flip strategy are proposed to shed light on reliable ReRAM cross-point memory design.
Year
DOI
Venue
2015
10.1109/ASPDAC.2015.7058990
ASP-DAC
Keywords
Field
DocType
memory array reliability,integrated circuit reliability,random-access storage,temporal variation,cross-point resistive memory design,resistive ram,nonvolatile memory,integrated circuit design
Sense amplifier,Semiconductor memory,Interleaved memory,Computer science,Voltage drop,Electronic engineering,Computer memory,Memory refresh,Resistive random-access memory,Scalability
Conference
ISSN
Citations 
PageRank 
2153-6961
6
0.51
References 
Authors
5
3
Name
Order
Citations
PageRank
Yang Zheng121633.97
Cong Xu2115448.25
Yuan Xie36430407.00