Title
7.2 A 128Gb 3b/cell V-NAND flash memory with 1Gb/s I/O rate
Abstract
Most memory-chip manufacturers keep trying to supply cost-effective storage devices with high-performance characteristics such as smaller tPROG, lower power consumption and longer endurance. For many years, every effort has been made to shrink die size to lower cost and to improve performance. However, the previously used node-shrinking methodology is facing challenges due to increased cell-to-cell interference and patterning difficulties caused by decreasing dimension. To overcome these limitations, 3D-stacking technology has been developed. As a result of long and focused research in 3D stacking technology, 128Gb 2b/cell device with 24 stack WL layers was announced in 2014 [1].
Year
DOI
Venue
2015
10.1109/ISSCC.2015.7062960
ISSCC
Keywords
Field
DocType
v-nand flash memory,3d-stacking technology,cell-to-cell interference,logic design,cost-effective storage devices,flash memories,programming,computer architecture
Nand flash memory,Flash file system,Computer science,Electronic engineering,Input/output,Interference (wave propagation),Electrical engineering,Charge trap flash,Stacking,Power consumption
Conference
Citations 
PageRank 
References 
9
0.81
2
Authors
34
Name
Order
Citations
PageRank
Jae-Woo Im191.48
Woopyo Jeong212914.49
Doo-Hyun Kim315533.21
Sangwan Nam4253.12
Dong-Kyo Shim5454.71
Myung-Hoon Choi6455.05
Hyun-Jun Yoon7636.52
Dae-Han Kim891.14
Youse Kim9203.12
Hyun Wook Park1049554.79
Dong-Hun Kwak11252.44
Sang-Won Park12253.80
Seok-Min Yoon1391.14
Wook-Ghee Hahn14418.19
Jinho Ryu15807.73
Sang-Won Shim16374.17
Kyung-Tae Kang17333.61
Sungho Choi1814519.00
Jeong-Don Ihm196510.22
Young-Sun Min20414.50
In-Mo Kim21435.20
Doosub Lee22424.70
Ji-Ho Cho23182.40
Oh-Suk Kwon24345.38
Ji-Sang Lee25293.70
Moosung Kim26607.39
Sang-Hyun Joo27696.60
Jae-hoon Jang28131.98
Sang-Won Hwang2991.14
Dae-Seok Byeon307811.94
Hyang-Ja Yang31425.06
Ki-Tae Park3219719.35
Kyehyun Kyung3314218.84
Jeong-Hyuk Choi34598.17