Title
A Process-Variation Resilient Current Mode Logic With Simultaneous Regulations for Time Constant, Voltage Swing, Level Shifting, and DC Gain Using Time-Reference-Based Adaptive Biasing Chain
Abstract
A process-variation resilient current mode logic (CML) is presented. The proposed CML employs time-reference-based adaptive biasing chain with replica load to address performance degradation over the process variations. It adjusts variable load resistor to simultaneously regulate time constant, voltage swing, level shifting, and DC gain. The prototype demonstrates the process-variation resiliency of the proposed solution by showing performance degradation over the process corners. Over 20% of polygate resistance variation, the proposed CML suppresses the degradation of speed and rms jitter less than 4.3% and 0.15 ps while conventional CML results in 13% and 3.8-ps degradation, respectively.
Year
DOI
Venue
2015
10.1109/TVLSI.2014.2301034
IEEE Trans. VLSI Syst.
Keywords
Field
DocType
frequency divider,process variation,prbs generator,variable resistor,dc gain regulation,variable load resistor,cml,bang-bang phase detector (bbpd),polygate resistance variation,current-mode logic,switched capacitor (sc),time constant regulation,self-oscillation frequency,bang???bang phase detector (bbpd),level shifting regulation,current mode logic (cml),performance degradation,time constant,time 3.8 ps,time-reference-based adaptive biasing chain,variable resistor.,time 0.15 ps,process-variation resilient current mode logic,voltage swing regulation,generators,resistors,capacitance,jitter
Capacitance,Process corners,Computer science,Control theory,Electronic engineering,Resistor,Process variation,Jitter,Current-mode logic,Time constant,Biasing
Journal
Volume
Issue
ISSN
23
1
1063-8210
Citations 
PageRank 
References 
0
0.34
4
Authors
3
Name
Order
Citations
PageRank
Hyung-Joon Jeon1102.65
José Silva-Martínez226739.39
Sebastian Hoyos323429.24