Sebastian Hoyos - Citegraph

Author Info

Name	Affiliation	Papers
SEBASTIAN HOYOS	Dept. of Electr. Eng. & Comput. Sci., Univ. of California, Berkeley, CA, USA	49
Collaborators	Citations	PageRank
84	234	29.24
Referers	Referees	References
591	840	394

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100840

Publications (49 rows)

Collaborators (84 rows)

Referers (100 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
A 38GS/s 7b Time-Interleaved Pipelined-SAR ADC with Speed-Enhanced Bootstrapped Switch in 22nm FinFET	0	0.34	2022
A Jitter-Robust 40Gb/s ADC-Based Multicarrier Receiver Front End in 22nm FinFET	0	0.34	2022
Special Issue on the 2022 IEEE International Symposium on Circuits and Systems	0	0.34	2022
Recurrent Neural Network Equalization for Wireline Communication Systems	0	0.34	2022
A 1.5GS/s 8b Pipelined-SAR ADC with Output Level Shifting Settling Technique in 14nm CMOS	2	0.51	2020
Kalman-Based Real-Time Functional Decomposition for the Spectral Calibration in Swept Source Optical Coherence Tomography.	0	0.34	2020
Jitter-Robust Multicarrier ADC-Based Serial Link Receiver Architecture - (Invited Special Session Paper).	0	0.34	2019
A 52-Gb/s ADC-Based PAM-4 Receiver With Comparator-Assisted 2-bit/Stage SAR ADC and Partially Unrolled DFE in 65-nm CMOS	2	0.37	2019
Blocker-Tolerant RF-to-Digital Linearization With a Very Nonlinear Auxiliary Path	0	0.34	2019
A 32 Gb/s ADC-based PAM-4 receiver with 2-bit/stage SAR ADC and partially-unrolled DFE	1	0.48	2018
The Spectral Calibration of Swept-Source Optical Coherence Tomography Systems Using Unscented Kalman Filter	0	0.34	2018
A 25 GS/s 6b TI Two-Stage Multi-Bit Search ADC With Soft-Decision Selection Algorithm in 65 nm CMOS.	1	0.36	2017
Compressed Level Crossing Sampling for Ultra-Low Power IoT Devices.	1	0.35	2017
Towards an on-chip signal processing solution for the online calibration of SS-OCT systems	1	0.35	2017
A novel continuous time ternary encoding based SS-OCT calibration	0	0.34	2016
CMOS ADC-based receivers for high-speed electrical and optical links.	2	0.50	2016
A 10 Gb/s Hybrid ADC-Based Receiver With Embedded Analog and Per-Symbol Dynamically Enabled Digital Equalization.	6	0.79	2016
Compressed Power Spectral Density Estimation via Group-Based Total Variation Minimization	0	0.34	2016
A 35 dBm Output Power and 38 dB Linear Gain PA With 44.9% Peak PAE at 1.9 GHz in 40 nm CMOS.	3	0.57	2016
3.6 A 10Gb/s hybrid ADC-based receiver with embedded 3-tap analog FFE and dynamically-enabled digital equalization in 65nm CMOS	2	0.43	2015
A Process-Variation Resilient Current Mode Logic With Simultaneous Regulations for Time Constant, Voltage Swing, Level Shifting, and DC Gain Using Time-Reference-Based Adaptive Biasing Chain	0	0.34	2015
A 25GS/s 6b TI binary search ADC with soft-decision selection in 65nm CMOS	4	0.50	2015
A 6 bit 10 GS/s TI-SAR ADC With Low-Overhead Embedded FFE/DFE Equalization for Wireline Receiver Applications	1	0.41	2014
Compressed Digital Beamformer with asynchronous sampling for ultrasound imaging	4	0.46	2013
Asynchronous Binary Compressive Sensing for Wireless Body Sensor Networks	0	0.34	2013
Digital-Assisted Asynchronous Compressive Sensing Front-End	6	0.48	2012
Sensitivity Analysis of Continuous-Time Δ Σ ADCs to Out-of-Band Blockers in Future SAW-Less Multi-Standard Wireless Receivers.	6	0.55	2012
Least mean squared Background Calibration for OFDM Multichannel Receivers.	0	0.34	2012
The impact of ADC nonlinearity in a mixed-signal compressive sensing system for frequency-domain sparse signals.	5	0.74	2012
A 15 MHz to 600 MHz, 20 mW, 0.38 mm2 Split-Control, Fast Coarse Locking Digital DLL in 0.13 µ m CMOS.	0	0.34	2012
A Sub-Nyquist Rate Compressive Sensing Data Acquisition Front-End	5	0.57	2012
Analytical framework and bandwidth optimisation of orthogonal frequency division multiplexing low-order multi-channel filter-bank receivers for achieving sampling clock-jitter robustness.	0	0.34	2011
Sensitivity analysis of pulse-width jitter induced noise in continuous-time delta-sigma modulators to out-of-band blockers in wireless receivers	2	0.40	2011
Corrections to “A Sub-Nyquist Rate Sampling Receiver Exploiting Compressive Sensing” [Mar 11 507-520]	0	0.34	2011
Corrections to "A Sub-Nyquist Rate Sampling Receiver Exploiting Compressive Sensing".	0	0.34	2011
A Sub-Nyquist Rate Sampling Receiver Exploiting Compressive Sensing	36	2.09	2011
Clock-Jitter-Tolerant Wideband Receivers: An Optimized Multichannel Filter-Bank Approach	6	0.47	2011
A Multiphase Multipath Technique With Digital Phase Shifters for Harmonic Distortion Cancellation	4	0.64	2010
A Sixth-Order 200 MHz IF Bandpass Sigma-Delta Modulator With Over 68 dB SNDR in 10 MHz Bandwidth	20	2.21	2010
Mixed-Signal Parallel Compressive Spectrum Sensing for Cognitive Radios	11	1.10	2010
A 1.8v, Sub-Mw, Over 100% Locking Range, Divide-By-3 And 7 Complementary-Injection-Locked 4 Ghz Frequency Divider	3	0.69	2009
Compressive spectrum sensing front-ends for cognitive radios	6	0.50	2009
Mixed-signal parallel compressed sensing and reception for cognitive radio	60	2.92	2008
A 15 MHz – 600 MHz, 20 mW, 0.38 mm 2 , fast coarse locking digital DLL in 0.13μm CMOS	0	0.34	2008
Applications of Multipath Transform-Domain Charge-Sampling Wide-Band Receivers	7	0.53	2008
Ultra-Wideband Analog-to-Digital Conversion Via Signal Expansion	20	1.63	2005
Ultra-Wideband Multicarrier Communication Receiver Based On Analog To Digital Conversion In The Frequency Domain	0	0.34	2005
High-speed A/D conversion for ultra-wideband signals based on signal projection over basis functions.	6	0.76	2004
Mixed-signal equalization architectures for printed circuit board channels.	1	0.50	2002