Name
Abstract | ||
|---|---|---|
In this work, a new verification method for the power-down mode of analog circuit blocks is presented. In power-down mode, matched transistors can be stressed with asymmetric voltages. This will cause time-dependent mismatch due to transistor aging. In order to avoid reliability problems, a new method for automatic detection of asymmetric power-down stress conditions is presented. Therefore, power-down voltage-matching rules are formulated. The method combines structural analysis and voltage propagation. Experimental results demonstrate the efficiency and effectiveness of the approach. |
Year | Venue | Keywords |
|---|---|---|
2015 | DATE | reliability,analog circuits,structural analysis,ageing,logic gates,aging,transistors |
Field | DocType | ISSN |
Stress conditions,Computer science,Voltage,Transistor aging,Electronic engineering,Field-programmable analog array,Transistor,Electrical engineering,Analog to digital conversion | Conference | 1530-1591 |
Citations | PageRank | References |
3 | 0.65 | 4 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Michael Zwerger | 1 | 7 | 2.54 |
| Helmut E. Graeb | 2 | 269 | 36.22 |