Name
Abstract | ||
|---|---|---|
Shared-memory chip-multi-processor (CMP) architectures define memory consistency models that establish the ordering rules for memory operations from multiple threads. Validating the correctness of a CMP’s implementation of its memory consistency model requires extensive monitoring and analysis of memory accesses while multiple threads are executing on the CMP. In this work, we present a low overhead solution for observing, recording and analyzing shared-memory interactions for use in an emulation and/or post-silicon validation environment. Our approach leverages portions of the CMP’s own data caches, augmented only by a small amount of hardware logic, to log information relevant to memory accesses. After transferring this information to a central memory location, we deploy our own analysis algorithm to detect any possible memory consistency violations. We build on the property that a violation corresponds to a cycle in an appropriately defined graph representing memory interactions. The solution we propose allows a designer to choose where to run the analysis algorithm: i) on the CMP itself, ii) on a separate processor residing on the validation platform or iii) off-line on a separate host machine. Our experimental results show an 83% bug detection rate, in our testbed CMP, over three distinct memory consistency models, namely: relaxed-memory order (RMO), total-store order (TSO) and sequential consistency (SC). Finally, note that our solution can be disabled in the final product, leading to zero performance overhead and a per-core area overhead that is smaller than the size of a physical integer register file in a modern processor. |
Year | DOI | Venue |
|---|---|---|
2015 | 10.1109/TCAD.2015.2402171 | Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions |
Keywords | Field | DocType |
Cache memory,Emulation,Memory architecture,Multiprocessor interconnection,Post-silicon validation | Registered memory,Interleaved memory,Shared memory,Computer science,Parallel computing,Distributed memory,Real-time computing,Memory management,Memory map,Consistency model,Cache coherence,Embedded system | Journal |
Volume | Issue | ISSN |
PP | 99 | 0278-0070 |
Citations | PageRank | References |
4 | 0.42 | 20 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Biruk W. Mammo | 1 | 4 | 0.42 |
| Valeria Bertacco | 2 | 1365 | 86.93 |
| Andrew DeOrio | 3 | 315 | 14.34 |
| Ilya Wagner | 4 | 204 | 10.01 |