Name
Abstract | ||
|---|---|---|
This paper presents a novel technique that modifies automatic test pattern generation test patterns to reduce time-averaged IR drop of a test pattern. We propose a fast average IR drop estimation, which is very close to the time-averaged IR drop of time-consuming transient simulation (R² = 0.99). We calculate the contribution of every node to these nodes inside IR-drop hotspot so that we can effectively modify only a few don't care bits in the test patterns to reduce IR drop. The experimental results show that our technique successively reduces time-averaged IR drop by 10% with almost no fault coverage loss and no test pattern inflation. |
Year | DOI | Venue |
|---|---|---|
2016 | 10.1109/TVLSI.2015.2391291 | VLSI) Systems, IEEE Transactions |
Keywords | Field | DocType |
ir drop,low-power testing,test pattern modification.,logic gates,automatic test pattern generation | Automatic test pattern generation,Logic gate,Power network design,Fault coverage,Simulation,Computer science,Electronic engineering,Real-time computing,Transient analysis,Hotspot (Wi-Fi) | Journal |
Volume | Issue | ISSN |
PP | 99 | 1063-8210 |
Citations | PageRank | References |
2 | 0.40 | 29 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Wei-Sheng Ding | 1 | 2 | 0.40 |
| Hung-Yi Hsieh | 2 | 17 | 4.22 |
| Cheng-Yu Han | 3 | 2 | 0.40 |
| James Chien-Mo Li | 4 | 187 | 27.16 |
| Xiaoqing Wen | 5 | 790 | 77.12 |