Name
Abstract | ||
|---|---|---|
With memory contributing to a significant fraction of the overall power consumption, several power management techniques targeting the memory sub-system have been proposed by researchers. In this work, we propose two memory power optimization techniques. We first suggest dynamically varying the queue structure in a memory controller, and next propose an adaptive threshold technique for switching to low power SELF-REFRESH operating mode of the DDR3 SDRAM. With the proposed queue-resizing optimization, the power consumption reduces by up to 93%, while the adaptive threshold technique results in an additional 21% power savings, on an average, over a constant threshold implementation. |
Year | DOI | Venue |
|---|---|---|
2015 | 10.1109/VLSID.2015.59 | VLSI Design |
Field | DocType | ISSN |
Power management,Power optimization,Memory bandwidth,Computer science,Queue,Real-time computing,Electronic engineering,CAS latency,Memory controller,DDR3 SDRAM,Memory refresh | Conference | 1063-9667 |
Citations | PageRank | References |
0 | 0.34 | 10 |
Authors | ||
6 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Preeti Ranjan Panda | 1 | 786 | 89.40 |
| Vishal Patel | 2 | 103 | 12.68 |
| Praxal Shah | 3 | 0 | 0.34 |
| Namita Sharma | 4 | 15 | 3.74 |
| Vaidyanathan Srinivasan | 5 | 0 | 0.34 |
| Dipankar Sarma | 6 | 14 | 1.29 |