Title | ||
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Adaptive Cache Coherence Mechanisms with Producer–Consumer Sharing Optimization for Chip Multiprocessors |
Abstract | ||
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In chip multiprocessors (CMPs), maintaining cache coherence can account for a major performance overhead. Write-invalidate protocols adapted by most CMPs generate high cache-to-cache misses under producer-consumer sharing patterns. Accordingly, this paper presents three cache coherence mechanisms optimized for CMPs. First, to reduce coherence misses observed in write-invalidate-based protocols, we propose a dynamic write-update mechanism augmented on top of a write-invalidate protocol. This mechanism is specifically triggered at the detection of a producer-consumer sharing pattern. Second, we extend this adaptive protocol with a bandwidth-adaptive mechanism to eliminate performance degradation from write-updates under limited bandwidth. Finally, proximity-aware mechanism is proposed to extend the base adaptive protocol with latency-based optimizations. Experimental analysis is conducted on a set of scientific applications from the SPLASH-2 and NAS parallel benchmark suites. The proposed mechanisms were shown to reduce coherence misses by up to 48% and in return speed up application performance up to 30%. Bandwidth-adaptive mechanism is proven to perform well under varying levels of available bandwidth. Results from our proposed proximity-aware extension demonstrated up to 6% performance gain over the base adaptive protocol for 64-core tiled CMP runs. In addition, the analytical model provided good estimates for performance gains from our adaptive protocols. |
Year | DOI | Venue |
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2015 | 10.1109/TC.2013.217 | Computers, IEEE Transactions |
Keywords | Field | DocType |
cache storage,multiprocessing systems,parallel architectures,performance evaluation,64-core tiled cmp,nas parallel benchmark suites,splash-2 suites,adaptive cache coherence mechanisms,bandwidth-adaptive mechanism,base adaptive protocol,cache-to-cache misses,chip multiprocessors,dynamic write-update mechanism,latency-based optimizations,performance degradation,producer-consumer sharing optimization,producer-consumer sharing pattern,proximity-aware extension,write-invalidate-based protocols,cache coherence,adaptable architectures,chip multiprocessors (cmps),producer/consumer,optimization,bandwidth,producer consumer,radiation detectors,coherence,multicore processing,protocols | Computer architecture,Memory hierarchy,Computer science,MESI protocol,Parallel computing,Chip,Real-time computing,Coherence (physics),Bandwidth (signal processing),Multi-core processor,Speedup,Cache coherence | Journal |
Volume | Issue | ISSN |
64 | 2 | 0018-9340 |
Citations | PageRank | References |
3 | 0.41 | 32 |
Authors | ||
3 |
Name | Order | Citations | PageRank |
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Abdullah Kayi | 1 | 40 | 4.80 |
Olivier Serres | 2 | 65 | 7.52 |
Tarek El-Ghazawi | 3 | 427 | 44.88 |