Name
Abstract | ||
|---|---|---|
Heterogeneous architectures with single-instruction set architecture (ISA) asymmetric cores can improve both the performance and energy efficiency of software execution by dynamically selecting the most appropriate core type to run each execution thread. In this paper, we propose a trace-based methodology to explore power and performance benefits of single-ISA heterogeneous core architectures. The basic idea is to collect multiple traces by running a workload on different homogeneous platforms, and to align these traces for offline analysis. For this, we propose a wavelet-based similarity metric, which captures both fine-grain and coarse-grain software phases across different traces. Then, we propose a scalable dynamic programming algorithm to optimize this metric to align the traces. Our experiments show that the runtime and energy values predicted by our offline methodology have good accuracy with respect to the real measurements from a prototype heterogeneous system. |
Year | DOI | Venue |
|---|---|---|
2015 | 10.1109/TCAD.2014.2387856 | Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions |
Keywords | DocType | Volume |
Heterogeneous architectures,heterogeneous architectures,system level CAD,system-level CAD,trace alignment,trace analysis | Journal | 34 |
Issue | ISSN | Citations |
3 | 0278-0070 | 0 |
PageRank | References | Authors |
0.34 | 12 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Muhammet Mustafa Ozdal | 1 | 313 | 23.18 |
| A. Jaleel | 2 | 1426 | 70.43 |
| Narvaez, P. | 3 | 0 | 0.34 |
| Burns, S. | 4 | 161 | 19.50 |