Name
Title | ||
|---|---|---|
Way Halted Prediction Cache: An Energy Efficient Cache Architecture for Embedded Processors |
Abstract | ||
|---|---|---|
This paper proposes a novel cache architecture -- Way Halted Prediction -- to reduce energy consumption and effective access time of set associative caches. This is achieved with the help of halt tag array and prediction circuit. Experimental evaluation of various SPEC benchmark programs on CACTI 5.3 and CASIM simulators reveal that the proposed architecture offers 33%, 6% and 3% savings in dynamic energy consumption and 1.80%, 6.13% and -1.95% saving in effective access time over conventional, way predicting and way halting cache architectures respectively. |
Year | DOI | Venue |
|---|---|---|
2015 | 10.1109/VLSID.2015.16 | VLSI Design |
Keywords | Field | DocType |
cache storage,circuit simulation,content-addressable storage,embedded systems,energy consumption,microprocessor chips,cacti 5.3 simulator,casim simulator,spec benchmark program,dynamic energy consumption,embedded processor,energy efficient cache architecture,halt tag array,halting cache architecture,prediction circuit,set associative cache,way halted prediction cache,cache architecture,energy efficient cache design,way halting,way predicting | Cache invalidation,Cache pollution,Computer science,Cache,Parallel computing,Real-time computing,Cache algorithms,Page cache,Cache coloring,Bus sniffing,Smart Cache | Conference |
ISSN | Citations | PageRank |
1063-9667 | 0 | 0.34 |
References | Authors | |
10 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Neethu Bal Mallya | 1 | 0 | 0.34 |
| Geeta Patil | 2 | 1 | 1.03 |
| Biju K Raveendran | 3 | 2 | 5.10 |