Biju K Raveendran - Citegraph

Author Info

Name	Affiliation	Papers
BIJU K RAVEENDRAN	BITS Pilani, Rajasthan, India	15
Collaborators	Citations	PageRank
28	2	5.10
Referers	Referees	References
5	264	106

Search Limit

100264

Publications (15 rows)

Collaborators (28 rows)

Referers (5 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
MOESI L : A Cache Coherency Protocol for Locked Mixed Criticality L1 Data Cache	0	0.34	2021
Dpvfs: A Dynamic Procrastination Cum Dvfs Scheduler For Multi-Core Hard Real-Time Systems	0	0.34	2019
Moesif: A Mc/Mp Cache Coherence Protocol With Improved Bandwidth Utilisation	0	0.34	2019
MEDIATOR - A Mixed Criticality Deadline Honored Arbiter for Multi-core Real-time Systems	0	0.34	2019
SMILEY - A Mixed-Criticality Real-Time Task Scheduler for Multicore Systems.	0	0.34	2018
LAMCS: A leakage aware DVFS based mixed task set scheduler for multi-core processors	0	0.34	2017
Energy Efficient Real-Time Scheduling Algorithm For Mixed Task Set On Multi-Core Processors	1	0.35	2017
DTLB: Deterministic TLB for Tightly Bound Hard Real-Time Systems	0	0.34	2017
eduCloud: a VM communication aware, migration efficient cloud for scientific computing.	0	0.34	2017
Way Halted Prediction Cache: An Energy Efficient Cache Architecture for Embedded Processors	0	0.34	2015
Evaluation of priority based real time scheduling algorithms: choices and tradeoffs	0	0.34	2008
An Energy Efficient Selective Placement Scheme for Set-Associative Data Cache in Embedded System	0	0.34	2007
EFFS: Efficient Flash File System for Wireless Sensor Nodes	0	0.34	2007
Variants of priority scheduling algorithms for reducing context-switches in real-time systems	1	0.36	2006
A context-switch reduction heuristic for power-aware off-line scheduling	0	0.34	2006

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