Name
Title | ||
|---|---|---|
On Improving Interconnect Defect Diagnosis Resolution and Yield for Interposer-Based 3-D ICs |
Abstract | ||
|---|---|---|
This article discusses a design-for-test (DFT) architecture for detecting and repairing faulty interconnects in 3-D IC circuits utilizing through silicon via (TSV) and interposer technology. The yield of such circuits depends highly on the ability to have functioning interconnects which connect the various dies. The authors also propose a built-in-self-test (BIST) framework to enable at-speed testing of such interconnects. |
Year | DOI | Venue |
|---|---|---|
2014 | 10.1109/MDAT.2014.2304437 | IEEE Design & Test |
Keywords | Field | DocType |
yield enhancement,integrated circuit testing,design-for-test architecture,tsv,integrated circuit interconnections,3d ic circuit,through silicon via technology,bist framework,defect diagnosis resolution interconnection,interconnect bist,three-dimensional integrated circuits,dft architecture,built-in self test,tsv technology,fault diagnosis,interconnect repair,interposer test,defect diagnosis,design for testability,interposer technology,built-in-self-test framework,3d-ic | Computer science,Electronic engineering,Through-silicon via,Interposer,Redundancy (engineering),Three-dimensional integrated circuit,Electronic circuit,Interconnection,Computer engineering,Maintenance engineering,Built-in self-test | Journal |
Volume | Issue | ISSN |
31 | 4 | 2168-2356 |
Citations | PageRank | References |
1 | 0.37 | 5 |
Authors | ||
6 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Chun-Chuan Chi | 1 | 117 | 8.81 |
| Lin, Bing-Yang | 2 | 14 | 4.59 |
| Wu, Cheng-Wen | 3 | 1843 | 170.44 |
| Min-Jer Wang | 4 | 55 | 9.57 |
| Lin, Hung-Chih | 5 | 118 | 13.03 |
| Ching-Nen Peng | 6 | 27 | 3.65 |