Title | ||
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Design Methodology for Highly Reliable, High Performance ReRAM and 3-Bit/Cell MLC NAND Flash Solid-State Storage |
Abstract | ||
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This paper proposes design methodology for highly reliable, high performance ReRAM and 3-bit/cell multi-level cell (MLC) NAND flash solid-state storage. Six techniques, calibrated RRef (CR), flexible RRef (FR), adaptive asymmetric coding (AAC), verify trials reduction (VTR), bits/cell optimization (BCO), and balanced RAID-5/6 are proposed. CR, FR, AAC, and VTR are for ReRAM. CR and FR change the read-reference resistance (RRef) to reduce the BER. AAC first increases the population of Set and then Reset. The BER reduction with FR and AAC is 69 and 78% with 60 and 75% asymmetry, respectively. In VTR, by changing the number of acceptable bit-errors, the total Reset time is reduced by 97% at maximum with small ECC calculation overhead. The reliability of 3-bit/cell MLC NAND flash memory is improved by BCO and balanced RAID-5/6. BCO reallocates 3-bit/cell MLC to 2-bit/cell MLC and single-level cell (SLC) and the write/erase cycle increases by over 22-times. Balanced RAID-5/6 evenly allocates upper/middle/lower pages to a stripe to reduce the RAID failure rate by 98%. |
Year | DOI | Venue |
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2015 | 10.1109/TCSI.2014.2370171 | IEEE Trans. on Circuits and Systems |
Keywords | Field | DocType |
encoding,reram,reliability,logic design,resistance,ber,bit error rate,performance,resistive ram | Flash file system,NAND gate,Design methods,Computer hardware,Solid-state storage,Mathematics,Bit cell,Resistive random-access memory | Journal |
Volume | Issue | ISSN |
62 | 3 | 1549-8328 |
Citations | PageRank | References |
2 | 0.37 | 12 |
Authors | ||
5 |
Name | Order | Citations | PageRank |
---|---|---|---|
Shuhei Tanakamaru | 1 | 121 | 18.35 |
Hiroki Yamazawa | 2 | 9 | 1.44 |
Tsukasa Tokutomi | 3 | 20 | 3.23 |
Sheyang Ning | 4 | 11 | 2.95 |
Ken Takeuchi | 5 | 3 | 0.77 |