Name
Abstract | ||
|---|---|---|
This brief presents a simultaneous bidirectional capacitive coupling transceiver for intertier communication in 3-D integrated circuits. A novel capacitive coupling interconnect structure is proposed. Optimization of the proposed interconnect structure for minimizing parasitic capacitance achieves the voltage swing VSW of 200 mV at the voltage sensing nodes. The data rate of 3 Gb/s/ch is demonstrated in the emulated-3D interconnect. The proposed transceiver consumes 140 μW at 3 Gb/s/ch. The test chip was fabricated in a 65-nm CMOS technology. |
Year | DOI | Venue |
|---|---|---|
2014 | 10.1109/TCSII.2014.2335426 | IEEE Trans. on Circuits and Systems |
Keywords | Field | DocType |
voltage swing,simultaneous bidirectional,cmos integrated circuits,transceivers,four-level signaling,capacitive coupling interconnect structure,voltage sensing nodes,voltage 200 mv,size 65 nm,parasitic capacitance,three-dimensional integrated circuits,3dics,intertier communication,3d integrated circuits,cmos technology,three-dimensional integrated circuits (3dics),simultaneous bidirectional transceiver,capacitive coupling transceiver,power 140 muw,transceiver | Parasitic capacitance,Coupling,Transceiver,Voltage,Electronic engineering,Chip,CMOS,Electrical engineering,Integrated circuit,Capacitive coupling,Mathematics | Journal |
Volume | Issue | ISSN |
61 | 9 | 1549-7747 |
Citations | PageRank | References |
2 | 0.39 | 9 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Myat Thu Linn Aung | 1 | 11 | 2.69 |
| Eric Lim | 2 | 6 | 0.88 |
| Takefumi Yoshikawa | 3 | 18 | 6.62 |
| Tae-hyoung Kim | 4 | 163 | 35.19 |