Takefumi Yoshikawa - Citegraph

Author Info

Name	Affiliation	Papers
TAKEFUMI YOSHIKAWA	Oanason Corp, Mixed Signal Technol Dev Div, Tokyo, Japan	15
Collaborators	Citations	PageRank
30	18	6.62
Referers	Referees	References
47	155	60

Search Limit

100155

Publications (15 rows)

Collaborators (30 rows)

Referers (47 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
Session 23 overview: DRAM, MRAM & DRAM interfaces.	0	0.34	2017
Yield Enhancement of Face-to-Face Cu-Cu Bonding With Dual-Mode Transceivers in 3DICs.	1	0.34	2017
2.31-Gb/s/ch Area-Efficient Crosstalk Canceled Hybrid Capacitive Coupling Interconnect for 3-D Integration.	3	0.42	2016
F2: Memory trends: From big data to wearable devices	1	0.35	2015
Session 17 overview: Embedded memory and DRAM I/O: Memory subcommittee	0	0.34	2015
A Jitter Suppression Technique Against Data Pattern Dependency On High-Speed Interfaces For Highly Integrated Socs	0	0.34	2014
A 3-Gb/s/ch Simultaneous Bidirectional Capacitive Coupling Transceiver for 3DICs	2	0.39	2014
Design of self-biased fully differential receiver and crosstalk cancellation for capacitive coupled vertical interconnects in 3DICs	1	0.36	2013
Design of Simultaneous Bi-Directional Transceivers Utilizing Capacitive Coupling for 3DICs in Face-to-Face Configuration.	4	0.49	2012
Design of capacitive-coupling-based simultaneously bi-directional transceivers for 3DIC.	0	0.34	2011
An ultra-wide range Bi-directional transceiver with adaptive power control using background replica VCO gain calibration	2	1.00	2011
Current-Mode Transceiver With Nonfeedback Clock Recovery Capability For Mobile Applications	1	0.63	2008
Transceiver Macro With Spread-Spectrum Clocking Capability For Ac-Coupled Cable Interfaces	0	0.34	2008
An over-1-Gb/s transceiver core for integration into large system-on-chips for consumer electronics	1	0.40	2008
A Spread Spectrum Clock Generator Using Digital Tracking Scheme	2	0.54	2005

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