Name
Title | ||
|---|---|---|
Improving Small-Delay Fault Coverage Of On-Chip Delay Measurement By Segmented Scan And Test Point Insertion |
Abstract | ||
|---|---|---|
With IC design entering the nanometer scale integration, the reliability of VLSI has declined due to small-delay defects, which are hard to detect by traditional delay fault testing. To detect small-delay defects, on-chip delay measurement, which measures the delay time of paths in the circuit under test (CUT), was proposed. However, our pre-simulation results show that when using on-chip delay measurement method to detect small-delay defects, test generation under the single-path sensitization is required. This constraint makes the fault coverage very low. To improve fault coverage, this paper introduces techniques which use segmented scan and test point insertion (TPI). Evaluation results indicate that we can get an acceptable fault coverage, by combining these techniques for launch off shift (LOS) testing under the single-path sensitization condition. Specifically, fault coverage is improved 27.02 similar to 47.74% with 6.33 similar to 12.35% of hardware overhead. |
Year | DOI | Venue |
|---|---|---|
2014 | 10.1587/transinf.2014EDP7110 | IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS |
Keywords | Field | DocType |
small-delay defects, fault coverage, segmented scan, control point, observation point | Computer vision,Control point,Fault coverage,Computer science,Artificial intelligence,Computer hardware,Test point insertion | Journal |
Volume | Issue | ISSN |
E97D | 10 | 1745-1361 |
Citations | PageRank | References |
0 | 0.34 | 20 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Wenpo Zhang | 1 | 1 | 1.14 |
| Kazuteru Namba | 2 | 114 | 27.93 |
| Hideo Ito | 3 | 100 | 17.45 |