Name
Abstract | ||
|---|---|---|
The proposed stimulus design for linearity test is embedded in a differential successive approximation register analog-to-digital converter (SAR ADC), i.e. a design for testability (DFT). The proposed DFT is compatible to the pattern generator (P)) and output response analyzer (ORA) with the cost of 12.4-% area of the SAR ADC. The 10-bit SAR ADC prototype is verified in a 0.18-mu m CMOS technology and the measured differential nonlinearity (DNL) error is between -0.386 and 0.281 LSB at 1-MS/s. |
Year | DOI | Venue |
|---|---|---|
2014 | 10.1587/transele.E97.C.538 | IEICE TRANSACTIONS ON ELECTRONICS |
Keywords | Field | DocType |
analog-to-digital converter (ADC), design for testability (DFT), pattern generator (PG), output response analyzer (ORA) | Flight dynamics (spacecraft),Linearity,Electronic engineering,Engineering,Successive approximation ADC,Stimulus (physiology),Computer hardware | Journal |
Volume | Issue | ISSN |
E97C | 6 | 1745-1353 |
Citations | PageRank | References |
0 | 0.34 | 8 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| An-Sheng Chao | 1 | 2 | 1.07 |
| Cheng-Wu Lin | 2 | 75 | 6.09 |
| Hsin-Wen Ting | 3 | 41 | 8.81 |
| Soon-Jyh Chang | 4 | 655 | 73.67 |