Name
Abstract | ||
|---|---|---|
This study presents a systematic defect diagnosis to identify `culprit physical features' that are potentially responsible for yield loss. A `single location in-a-cluster' technique is proposed to diagnose multiple defects that may not be diagnosed by traditional `single location at-a-time' technique. A statistics technique, `analysis of variance', is conducted to reduce noise from random defects.... |
Year | DOI | Venue |
|---|---|---|
2014 | 10.1049/iet-cdt.2013.0104 | IET Computers & Digital Techniques |
Keywords | DocType | Volume |
fault diagnosis,integrated circuit layout,integrated circuit reliability,statistical analysis | Journal | 8 |
Issue | ISSN | Citations |
5 | 1751-8601 | 3 |
PageRank | References | Authors |
0.42 | 0 | 7 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Po-Juei Chen | 1 | 3 | 0.42 |
| Chieh-Chih Che | 2 | 3 | 0.42 |
| James Chien-Mo Li | 3 | 187 | 27.16 |
| Shuo-Fen Kuo | 4 | 9 | 0.95 |
| Pei-Ying Hsueh | 5 | 3 | 0.42 |
| Chun-Yi Kuo | 6 | 3 | 0.42 |
| Jih-Nung Lee | 7 | 14 | 3.13 |