Name
Title | ||
|---|---|---|
Benefits of Adding Hardware Support for Broadcast and Reduce Operations in MPSoC Applications |
Abstract | ||
|---|---|---|
MPI has been used as a parallel programming model for supercomputers and clusters and recently in MultiProcessor Systems-on-Chip (MPSoC). One component of MPI is collective communication and its performance is key for certain parallel applications to achieve good speedups. Previous work showed that, with synthetic communication-only benchmarks, communication improvements of up to 11.4-fold and 22-fold for broadcast and reduce operations, respectively, can be achieved by providing hardware support at the network level in a Network-on-Chip (NoC). However, these numbers do not provide a good estimation of the advantage for actual applications, as there are other factors that affect performance besides communications, such as computation. To this end, we extend our previous work by evaluating the impact of hardware support over a set of five parallel application kernels of varying computation-to-communication ratios. By introducing some useful computation to the performance evaluation, we obtain more representative results of the benefits of adding hardware support for broadcast and reduce operations. The experiments show that applications with lower computation-to-communication ratios benefit the most from hardware support as they highly depend on efficient collective communications to achieve better scalability. We also extend our work by doing more analysis on clock frequency, resource usage, power, and energy. The results show reasonable scalability for resource utilization and power in the network interfaces as the number of channels increases and that, even though more power is dissipated in the network interfaces due to the added hardware, the total energy used can still be less if the actual speedup is sufficient. The application kernels are executed in a 24-embedded-processor system distributed across four FPGAs. |
Year | DOI | Venue |
|---|---|---|
2014 | 10.1145/2629470 | TRETS |
Keywords | Field | DocType |
design,hardware/software interfaces,experimentation,parallel programming,fpga,multiprocessor,parallel computing,mpi,network-on-chip,performance,network on chip | Computer science,Real-time computing,Parallel programming model,Computer hardware,MPSoC,Speedup,Network interface,Distributed computing,Parallel computing,Network on a chip,Multiprocessing,Clock rate,Scalability,Embedded system | Journal |
Volume | Issue | ISSN |
7 | 3 | 1936-7406 |
Citations | PageRank | References |
6 | 0.75 | 10 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yuanxi Peng | 1 | 6 | 0.75 |
| Manuel Saldaña | 2 | 62 | 5.96 |
| Christopher Madill | 3 | 45 | 3.19 |
| Xiaofeng Zou | 4 | 6 | 0.75 |
| Paul Chow | 5 | 868 | 119.97 |