Name
Title | ||
|---|---|---|
A BIRA for Memories With an Optimal Repair Rate Using Spare Memories for Area Reduction |
Abstract | ||
|---|---|---|
The test cost and yield improvement of embedded memories have become very important as memory capacity and density have grown. For embedded memories, built-in redundancy analysis (BIRA) is widely used to improve yield by replacing faulty cells with a 2-D redundancy architecture. However, the most important factor in BIRA is the reduction of hardware overhead while keeping optimal repair rate. Most BIRA approaches require extra hardware overhead in order to store and analyze faults in the memory. These approaches do not utilize spare memories during the redundancy analysis (RA) procedure. However, the proposed BIRA minimizes area overhead by utilizing a part of the spare memory as an address mapping table (AMT). Since storing the faulty memory addresses take most of the extra hardware overhead, the reduced logical addresses produced by the AMT are used to reduce the extra hardware overhead. In addition, the reduced addresses are stored in content-addressable memories (CAMs) and used in the RA procedure. The proposed BIRA can achieve an optimal repair rate by using an exhaustive search RA algorithm. The proposed RA algorithm compares the repair solution candidates with all the fault addresses stored in the proposed CAMs to guarantee an exhaustive search. The experimental results show that the proposed BIRA requires a smaller area overhead than that of the previous state-of-the-art BIRA with an optimal repair rate. |
Year | DOI | Venue |
|---|---|---|
2014 | 10.1109/TVLSI.2013.2288637 | IEEE Transactions on Very Large Scale Integration Systems |
Keywords | Field | DocType |
address mapping table,optimal repair rate,built-in redundancy analysis,integrated circuit reliability,amt,faulty cells,test cost,exhaustive search ra algorithm,search problems,built-in redundancy analysis (bira),area overhead repair rate,spare memories,yield improvement,2d redundancy architecture,redundancy,bira,content-addressable memories,content-addressable storage,hardware overhead,memory capacity,built-in redundancy analysis (bira).,address mapping table (amt),fault analysis,embedded memories,cams,area reduction | Spare part,Brute-force search,Address mapping,% area reduction,Computer science,Real-time computing,Repair rate,Redundancy (engineering),Memory address,Computer hardware | Journal |
Volume | Issue | ISSN |
22 | 11 | 1063-8210 |
Citations | PageRank | References |
2 | 0.37 | 0 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Wooheon Kang | 1 | 22 | 3.46 |
| Hyungjun Cho | 2 | 104 | 8.44 |
| Joohwan Lee | 3 | 36 | 3.17 |
| Sungho Kang | 4 | 436 | 78.44 |