Name
Abstract | ||
|---|---|---|
Through-silicon vias (TSVs) provide high-density vertical interconnects between dies and enable the creation of 3-D ICs having higher performance and lower power consumption than traditional 2-D ICs. A practical TSV-based 3-D integration approach is to place multiple dies (or die stacks) side by side on a passive silicon interposer base, in which there are TSVs and metal wires serving as interconnects. In this paper, we propose a post-bond design-for-test architecture and a test strategy for such interposer-based 3-D ICs. Functional package pins and interconnects are reused to build multibit parallel test access mechanisms (PTAMs), which provide post-bond test access with no or low extra area costs. Four PTAM architectures are presented, and the corresponding PTAM optimization algorithms are proposed which can quickly identify the best PTAM configuration to achieve the shortest test time. We also propose an algorithm for adding dedicated test interconnects to improve test bandwidth at the expense of extra microbumps and metal wires. Experimental results show that the proposed techniques are effective in test length (and therefore test time) reduction. Moreover, cost-benefit analysis results suggest that our approaches have lower total test costs compared with a base-case one-bit JTAG-only solution. |
Year | DOI | Venue |
|---|---|---|
2014 | 10.1109/TVLSI.2013.2293192 | IEEE Transactions on Very Large Scale Integration Systems |
Keywords | Field | DocType |
cost-benefit analysis,through-silicon via (tsv).,optimisation,integrated circuit testing,integrated circuit interconnections,base-case one-bit jtag-only solution,power consumption,25-d ic,high-density vertical interconnection,functional package pins,three-dimensional integrated circuits,test access mechanism,metal wire,integrated circuit bonding,multibit parallel test access mechanism,passive silicon interposer base,interposer,optimization algorithm,3-d ic,silicon,microbumps,post-bond test,design for test,integrated circuit design,integrated circuit packaging,2.5-d ic,si,wires (electric),ptam architecture,passive networks,design for testability,elemental semiconductors,practical tsv-based 3d integration approach,3d ic,post-bond design-for-test architecture,through-silicon via (tsv),through-silicon vias,2d ic | Bond,Computer science,Silicon interposer,Electronic engineering,Three-dimensional integrated circuit,Physical design,Electrical engineering | Journal |
Volume | Issue | ISSN |
22 | 11 | 1063-8210 |
Citations | PageRank | References |
0 | 0.34 | 0 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Chun-Chuan Chi | 1 | 117 | 8.81 |
| Erik Jan Marinissen | 2 | 2053 | 170.58 |
| Sandeep Kumar Goel | 3 | 710 | 46.49 |
| Wu, Cheng-Wen | 4 | 1843 | 170.44 |