Name
Abstract | ||
|---|---|---|
This paper presents a representative random walk technique for fast transient IR-drop analysis. It selects only a small number of nodes to model the original network for simulation so that the memory and runtime are significantly reduced. Experimental results on benchmark circuits show that our proposed technique can be up to 330 times faster than a commercial simulator while the average error is less than 10%. Furthermore, the exhaustive simulation of all 26-K delay fault test patterns on a 400-K-gate design can be finished within a week. The proposed technique is very useful to simulate capture cycles for identifying the test patterns that cause excessive IR drop during at-speed testing. |
Year | DOI | Venue |
|---|---|---|
2014 | 10.1109/TVLSI.2013.2280616 | IEEE Transactions on Very Large Scale Integration Systems |
Keywords | Field | DocType |
400-k-gate design,transient ir-drop analysis,integrated circuit testing,at-speed testing,automatic test pattern generation,game theory,transient analysis.,delay fault test patterns,ir drop,representative random walk,transient analysis | Power network design,Random walk,Computer science,Simulation,Electronic engineering | Journal |
Volume | Issue | ISSN |
22 | 9 | 1063-8210 |
Citations | PageRank | References |
1 | 0.35 | 0 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Ming-Hong Tsai | 1 | 1 | 0.35 |
| Wei-Sheng Ding | 2 | 1 | 0.35 |
| Hung-Yi Hsieh | 3 | 17 | 4.22 |
| James Chien-Mo Li | 4 | 187 | 27.16 |