Title
A Delay Test Architecture for TSV With Resistive Open Defects in 3-D Stacked Memories
Abstract
The limits of technology scaling for smaller chip size, higher performance, and lower power consumption are being reached. For this reason, the memory semiconductor industry is searching for new technology. 3-D stacked memory using through-silicon via (TSV) has been considered as a promising solution for overcoming this challenge. However, to guarantee quality and yield for mass production of 3-D stacked memories, effective test techniques for TSV are required. In this paper, a new test architecture for testing TSVs in 3-D stacked memories is proposed. By comparing voltage changes generated due to resistive open defects with a reference voltage applied externally, the test circuit estimates delay across the TSV. This allows the possibility of a delay test with low-frequency test equipment. Experimental results demonstrate that the proposed test architecture can be effective in the testing of TSV with resistive open defects, and have lower area overhead and lower peak current consumption.
Year
DOI
Venue
2014
10.1109/TVLSI.2013.2289964
IEEE Transactions on Very Large Scale Integration Systems
Keywords
Field
DocType
integrated memory circuits,3-d stacked memories,integrated circuit testing,resistive open defects,voltage divider,voltage divider.,test circuit,delay circuits,test equipment,three-dimensional integrated circuits,delay test architecture,tsv testing,low-frequency test equipment,3d stacked memories,through-silicon via,through-silicon via (tsv),voltage dividers
Test equipment,Computer science,Resistive touchscreen,Voltage reference,Voltage,Electronic engineering,Chip size,Peak current,Electrical engineering,Semiconductor industry,Power consumption
Journal
Volume
Issue
ISSN
22
11
1063-8210
Citations 
PageRank 
References 
4
0.59
12
Authors
4
Name
Order
Citations
PageRank
Hyungsu Sung140.59
Keewon Cho2184.64
Kunsang Yoon340.59
Sungho Kang443678.44