Paper Info
Title
An Efficient Implementation of Montgomery Multiplication on Multicore Platform With Optimized Algorithm, Task Partitioning, and Network Architecture
Abstract
The modular multiplication (MM) is a key operation in cryptographic algorithms, such as RSA and elliptic-curve cryptography. Multicore processor is a suitable platform to implement MM because of its flexibility, high performance, and energy-efficiency. In this paper, we propose a block-level parallel algorithm for MM with quotient pipelining and optimally map it on a network-on-chip-based multicore platform equipped with broadcasting mechanism. Aiming at highest performance, a theoretical speedup model for parallel MM is also developed for parameter exploration that optimizes task partitioning. Experimental results based on a multicore prototype show that compared with the sequential MM on single core, the parallel implementation proposed in this paper maximizes the speedup ratio with regard to given intercore communication latency.
Year
DOI
Venue
2014
10.1109/TVLSI.2013.2294339
IEEE Transactions on Very Large Scale Integration Systems
Keywords
Field
DocType
block level parallel algorithm,multicast,cryptography,broadcast,quotient pipelining,multicore systems,montgomery multiplication,network-on-chip (noc),multiplying circuits,task partitioning,multicore processor,rsa,multiprocessing systems,parallel computing.,modular multiplication,public key cryptography,parallel computing,network architecture,intercore communication latency,elliptic curve cryptography,network-on-chip
Computer architecture,Montgomery reduction,Computer science,Parallel computing,Network architecture,Kochanski multiplication,Multi-core processor
Journal
Volume
Issue
ISSN
22
11
1063-8210
Citations 
PageRank 
References 
0
0.34
0
Authors
5
Name
Order
Citations
PageRank
Renfeng Dou100.34
Jun Han29124.48
Yifan Bo341.53
Zhiyi Yu415818.40
Xiaoyang Zeng5442107.26