Zhiyi Yu - Citegraph

Author Info

Name	Affiliation	Papers
ZHIYI YU	Univ Calif Davis, Dept Elect & Comp Engn, Davis, CA 95616 USA	29
Collaborators	Citations	PageRank
93	158	18.40
Referers	Referees	References
435	708	245

Search Limit

100708

Publications (29 rows)

Collaborators (93 rows)

Referers (100 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
A dual-rail/single-rail hybrid system using null convention logic circuits	0	0.34	2022
An Asynchronous Bundled-Data Template With Current Sensing Completion Detection Technique	0	0.34	2022
A Low-Power Asynchronous RISC-V Processor With Propagated Timing Constraints Method	1	0.36	2021
Balancing the Cost and Performance Trade-Offs in SNN Processors	0	0.34	2021
An MTJ-Based Asynchronous System With Extremely Fine-Grained Voltage Scaling	0	0.34	2021
High-parallelism Inception-like Spiking Neural Networks for Unsupervised Feature Learning	1	0.35	2021
A Data-Driven Asynchronous Neural Network Accelerator	1	0.36	2021
Hand gesture recognition algorithm combining hand-type adaptive algorithm and effective-area ratio for efficient edge computing	0	0.34	2021
NeuronLink: An Efficient Chip-to-Chip Interconnect for Large-Scale Neural Network Accelerators	0	0.34	2020
Spa: Stochastic Probability Adjustment For System Balance Of Unsupervised Snns	0	0.34	2020
A 68-mw 2.2 Tops/w Low Bit Width and Multiplierless DCNN Object Detection Processor for Visually Impaired People	2	0.36	2019
A Flexible and Energy-Efficient Convolutional Neural Network Acceleration With Dedicated ISA and Accelerator.	0	0.34	2018
A Scalable Network-on-Chip Microprocessor With 2.5D Integrated Memory and Accelerator.	2	0.40	2017
A 65 nm Cryptographic Processor for High Speed Pairing Computation	0	0.34	2015
A Heterogeneous Multicore Crypto-Processor With Flexible Long-Word-Length Computation	3	0.37	2015
Many-Core Processors Granularity Evaluation by Considering Performance, Yield, and Lifetime Reliability	1	0.35	2015
An Efficient Implementation of Montgomery Multiplication on Multicore Platform With Optimized Algorithm, Task Partitioning, and Network Architecture	0	0.34	2014
Low-Power Multicore Processor Design With Reconfigurable Same-Instruction Multiple Process	2	0.36	2014
A 65nm 39GOPS/W 24-core processor with 11Tb/s/W packet-controlled circuit-switched double-layer network-on-chip and heterogeneous execution array	17	1.24	2013
Parallelization of Radix-2 Montgomery Multiplication on Multicore Platform	2	0.40	2013
An 800MHz 320mW 16-core processor with message-passing and shared-memory inter-core communication mechanisms	12	1.47	2012
Evaluating Performance Of Manycore Processors With Various Granularities Considering Yield And Lifetime Reliability	4	0.39	2012
A low-area multi-link interconnect architecture for GALS chip multiprocessors	9	0.63	2010
High Performance, Energy Efficiency, and Scalability With GALS Chip Multiprocessors	10	0.63	2009
AsAP: An Asynchronous Array of Simple Processors	15	0.99	2008
Architecture and Evaluation of an Asynchronous Array of Simple Processors	3	0.49	2008
A scalable dual-clock FIFO for data transfers between arbitrary and haltable clock domains	28	1.18	2007
AsAP: A Fine-Grained Many-Core Platform for DSP Applications	14	0.88	2007
An asynchronous array of simple processors for dsp applications	31	3.80	2006