Name
Abstract | ||
|---|---|---|
This paper addresses the detection improvement of Gate Oxide Short defect using a delay test strategy. To achieve this objective, the concept of detectability interval is first introduced in the context of detection of short defects using Boolean test technique. Then this paradigm is extended to the detection of Gate Oxide Short defects using delay testing. Finally, it is shown that it is possible to significantly improve the detection of this kind of defect. |
Year | DOI | Venue |
|---|---|---|
2014 | 10.1515/itit-2013-1040 | IT-INFORMATION TECHNOLOGY |
Keywords | Field | DocType |
Logic circuits, Defect-Based test, Timing analysis, Test-pattern generation | Logic gate,Computer science,Algorithm,Electronic engineering,Static timing analysis,Gate oxide,Test strategy,Embedded system | Journal |
Volume | Issue | ISSN |
56 | 4 | 1611-2776 |
Citations | PageRank | References |
0 | 0.34 | 7 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jean Marc Gallière | 1 | 3 | 4.15 |
| F. Azaïs | 2 | 188 | 24.15 |
| Mariane Comte | 3 | 61 | 7.44 |
| Michel Renovell | 4 | 749 | 96.46 |