Name
Title | ||
|---|---|---|
Compact failure modeling for devices subject to electrostatic discharge stresses - A review pertinent to CMOS reliability simulation. |
Abstract | ||
|---|---|---|
This paper reviews the physical mechanisms and compact modeling approaches of two physical damages in MOS devices induced by electrostatic discharge (ESD) stresses; namely gate oxide breakdown and thermal failures. Theories underlying the failure mechanism are discussed and compact models that can be used to monitor ESD induced gate oxide breakdown and thermal failure are developed. Related work reported in the literature is discussed, and benchmarking of measurement data versus simulation results are included in support of the modeling work. |
Year | DOI | Venue |
|---|---|---|
2015 | 10.1016/j.microrel.2014.10.015 | Microelectronics Reliability |
Keywords | Field | DocType |
Electrostatic discharge (ESD),Gate oxide breakdown,Junction thermal failure,Thermal network,Transmission line pulsing (TLP),Transient power law (TPL) | Thermal,Electrostatic discharge,Electronic engineering,Thermal network,CMOS,Gate oxide,Engineering | Journal |
Volume | Issue | ISSN |
55 | 1 | 0026-2714 |
Citations | PageRank | References |
0 | 0.34 | 4 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Meng Miao | 1 | 0 | 0.68 |
| Yuanzhong (Paul) Zhou | 2 | 6 | 3.79 |
| Javier A. Salcedo | 3 | 3 | 3.54 |
| Jean-Jacques Hajjar | 4 | 2 | 2.20 |
| Juin J. Liou | 5 | 51 | 20.34 |