Juin J. Liou - Citegraph

Author Info

Name	Affiliation	Papers
JUIN J. LIOU	School of Electrical Engineering and Computer Science, University of Central Florida, Orlando, FL 32816, USA	39
Collaborators	Citations	PageRank
115	51	20.34
Referers	Referees	References
156	140	59

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100156

Publications (39 rows)

Collaborators (100 rows)

Referers (100 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
A double snapback SCR ESD protection scheme for 28 nm CMOS process.	0	0.34	2018
Statically triggered 3×VDD-Tolerant ESD detection circuit in a 90-nm low-voltage CMOS process.	0	0.34	2018
A review of DC extraction methods for MOSFET series resistance and mobility degradation model parameters.	1	0.41	2017
Tutorial sessions: Electrostatic discharge protection of consumer electronics: Challenges and solutions	0	0.34	2017
A novel vertical SCR for ESD protection in 40 V HV bipolar process.	0	0.34	2017
ESD protection structure with reduced capacitance and overshoot voltage for high speed interface applications.	0	0.34	2017
Very small snapback silicon-controlled rectifier for electrostatic discharge protection in 28 nm processing.	1	0.43	2016
Characteristics of ESD protection devices operated under elevated temperatures.	0	0.34	2016
Compact failure modeling for devices subject to electrostatic discharge stresses - A review pertinent to CMOS reliability simulation.	0	0.34	2015
Design and characterization of ESD solutions with EMC robustness for automotive applications	1	0.41	2015
A unified look at the use of successive differentiation and integration in MOSFET model parameter extraction.	1	0.39	2015
Total ionizing dose sensitivity of function blocks in FRAM.	0	0.34	2015
Design optimization of SiGe BiCMOS Silicon Controlled Rectifier for Charged Device Model (CDM) protection applications.	1	0.43	2014
Revisiting MOSFET threshold voltage extraction methods.	14	2.41	2013
Challenges on designing electrostatic discharge protection solutions for low power electronics.	0	0.34	2013
Integrated amorphous-Si TFT circuits for gate drivers on LCD panels	0	0.34	2013
vfTLP-VTH: A new method for quantifying the effectiveness of ESD protection for the CDM classification test.	0	0.34	2013
Novel ESD protection solution for single-ended mixer in GaAs pHEMT technology.	0	0.34	2013
Electrostatic discharge (ESD) protection of RF integrated circuits.	2	0.51	2012
A fully on-chip ESD protection UWB-band low noise amplifier using GaAs enhancement-mode dual-gate pHEMT technology.	0	0.34	2011
Thermal reliability of VCO using InGaP/GaAs HBTs.	1	0.39	2011
Self-protection capability of integrated NLDMOS power arrays in ESD pulse regimes	0	0.34	2011
Integration-based approach to evaluate the sub-threshold slope of MOSFETs	3	0.67	2010
Electro-thermal stress effect on InGaP/GaAs heterojunction bipolar low-noise amplifier performance	0	0.34	2010
Indirect fitting procedure to separate the effects of mobility degradation and source-and-drain resistance in MOSFET parameter extraction	2	0.55	2009
Investigation of diode geometry and metal line pattern for robust ESD protection applications	3	0.55	2008
Evaluation of RF electrostatic discharge (ESD) protection in 0.18-μm CMOS technology	1	0.37	2008
InGaP/GaAs heterojunction bipolar transistor and RF power amplifier reliability	1	0.40	2008
Reliability study of ultrathin oxide films subject to irradiation-then-stress treatment using conductive atomic force microscopy	0	0.34	2007
On-chip electrostatic discharge protection for CMOS gas sensor systems-on-a-chip (SoC)	1	0.67	2006
Novel electrostatic discharge protection structure for a monolithic gas sensor systems-on-a-chip	0	0.34	2005
An analytical threshold voltage model of NMOSFETs with hot-carrier induced interface charge effect	3	0.95	2005
Optimization of on-chip ESD protection structures for minimal parasitic capacitance	3	0.99	2003
Implementation of a comprehensive and robust MOSFET model in cadence SPICE for ESD applications	1	1.05	2002
Statistical modeling of MOS devices for parametric yield prediction	4	0.57	2002
Influence of polysilicon-gate depletion on the subthreshold behavior of submicron MOSFETs	3	0.87	2002
Semiconductor devices for RF applications: evolution and current status	4	0.88	2001
Testing the impact of process defects on ECL power-delay performance	0	0.34	1991
Statistical sensitivity simulation for integrating design and testing of MOSFET integrated circuits.	0	0.34	1991