Paper Info
Title
Automatic custom instruction identification for application-specific instruction set processors.
Abstract
The application-specific instruction set processors (ASIPs) have received more and more attention in recent years. ASIPs make trade-offs between flexibility and performance by extending the base instruction set of a general-purpose processor with custom functional units (CFUs). Custom instructions, executed on CFUs, make it possible to improve performance and achieve flexibility for extensible processors. The custom instruction synthesis flow involves two essential issues: custom instruction enumeration (subgraph enumeration) and custom instruction selection (subgraph selection). However, both enumerating all possible custom instructions of a given data-flow graph and selecting the most profitable custom instructions from the enumerated custom instructions are computationally difficult problems. In this paper, we propose efficient algorithms for custom instruction enumeration and custom instruction selection. Compared with previously proposed well-known enumeration algorithms, our approach can achieve a significant speedup while generating the identical set of all possible custom instructions or only connected custom instructions. Experimental results also show that a code size reduction rate up to 76% can be achieved for a set of computational intensive programs, and the speed-up achieved is up to 8.2×.
Year
DOI
Venue
2014
10.1016/j.micpro.2014.09.001
Microprocessors and Microsystems
Keywords
Field
DocType
Extensible processors,ASIPs,DFG,Custom instruction,Custom instruction enumeration,Custom instruction selection
Graph,Application specific,Computer architecture,Computer science,Instruction set,Parallel computing,Enumeration,Custom instruction,Code (cryptography),Extensibility,Speedup
Journal
Volume
Issue
ISSN
38
8
0141-9331
Citations 
PageRank 
References 
0
0.34
3
Authors
4
Name
Order
Citations
PageRank
Chenglong Xiao1294.70
Emmanuel Casseau200.68
Shanshan Wang341.38
Wanjun Liu4113.60