Name
Title | ||
|---|---|---|
A Joint Source/Channel Approach to Strengthen Embedded Programmable Devices against Flash Memory Errors |
Abstract | ||
|---|---|---|
Reconfigurable embedded systems can take advantage of programmable devices, such as microprocessors and field-programmable gate arrays (FPGAs), to achieve high performance and flexibility. Support to flexibility often comes at the expense of large amounts of nonvolatile memories. Unfortunately, nonvolatile memories, such as multilevel-cell (MLC) NAND flash, exhibit a high raw bit error rate that is mitigated by employing different techniques, including error correcting codes. Recent results show that low-density-parity-check (LDPC) codes are good candidates to improve the reliability of MLC NAND flash memories especially when page size increases. This letter proposes to use a joint source/channel approach, based on a modified arithmetic code and LDPC codes, to achieve both data compression and improved system reliability. The proposed technique is then applied to the configuration data of FPGAs and experimental results show the superior performance of the proposed system with respect to state of the art. Indeed, the proposed system can achieve bit-error-rates as low as about 10-8 for cell-to-cell coupling strength factors well higher than 1.0. |
Year | DOI | Venue |
|---|---|---|
2014 | 10.1109/LES.2014.2354454 | Embedded Systems Letters |
Keywords | Field | DocType |
multilevel cell,flash memory errors,low-density-parity-check (ldpc) coding,ldpc codes,microprocessors,modified arithmetic code,data compression,arithmetic coding,joint source/channel approach,error correction codes,low-density-parity-check,reconfigurable embedded systems,embedded programmable devices,nonvolatile memories,high raw bit error rate,fpga,mlc nand flash memories,system reliability,error correcting codes,field-programmable gate arrays (fpgas),field programmable gate arrays,error statistics,parity check codes,flash memories,embedded systems,computer architecture,bit error rate | Flash memory,Computer science,Low-density parity-check code,Parallel computing,Field-programmable gate array,Communication channel,NAND gate,Page,Computer hardware,Data compression,Bit error rate | Journal |
Volume | Issue | ISSN |
6 | 4 | 1943-0663 |
Citations | PageRank | References |
1 | 0.36 | 11 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Maurizio Martina | 1 | 268 | 45.20 |
| Carlo Condo | 2 | 132 | 21.40 |
| Guido Masera | 3 | 640 | 74.10 |
| Maurizio Zamboni | 4 | 289 | 41.76 |