Name
Abstract | ||
|---|---|---|
With the increasing non-recurring engineering cost of advanced process technologies, reconfigurable devices have received great attention in small and medium-volume integrated circuit designs. However, low logic diversity and slow timing performance limit the efficacy of field-programmable gate array (FPGA) and complex programmable logic device (CPLD). In this paper, we propose an efficient hybrid lookup table (LUT)/ sum-of-product (SOP) reconfigurable design style that exploits the advantages of circuit designs for both LUT cells and SOP cells. Then, architectural evaluations are performed to achieve the best cell ratio. Based on this architecture, we propose an efficient methodology for hybrid LUT/SOP logic synthesis that employs SOP-cell transformation, phase flipping, and phase duplication. The experimental results demonstrate that our proposed hybrid LUT/SOP design style achieves 35% circuit performance improvement and 52% transistor count reduction compared to the depth optimal 4-LUT-based FPGA. In comparison with the CPLD, our hybrid design style requires only 11% of the transistor count and reduces circuit delay by 11%. |
Year | Venue | Keywords |
|---|---|---|
2014 | JOURNAL OF INFORMATION SCIENCE AND ENGINEERING | hybrid FPGA,logic diversity analysis,logic synthesis,technology mapping,timing optimization |
Field | DocType | Volume |
Logic synthesis,Transistor count,Lookup table,Complex programmable logic device,Computer science,Field-programmable gate array,Gate array,Transistor,Computer hardware,Integrated circuit,Embedded system,Distributed computing | Journal | 30 |
Issue | ISSN | Citations |
1 | 1016-2364 | 1 |
PageRank | References | Authors |
0.36 | 0 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Po-Yang Hsu | 1 | 1 | 0.36 |
| Yung-Chih Chen | 2 | 413 | 39.89 |
| Yi-Yu Liu | 3 | 1 | 0.36 |