Name
Affiliation
Papers
YUNG-CHIH CHEN
Department of Computer Science, National Tsing Hua University, Hsinchu, Taiwan, R.O.C.
79
Collaborators
Citations 
PageRank 
134
413
39.89
Referers 
Referees 
References 
888
1045
699
Search Limit
1001000
Title
Citations
PageRank
Year
LOOPLock 2.0: An Enhanced Cyclic Logic Locking Approach00.342022
A High Voltage Driving Chiplet in Standard 0.18-<italic>μ</italic>m CMOS for Micro-Pixelated LED Displays Integrated With LTPS TFTs00.342022
On Synthesizing Memristor-Based Logic Circuits in Area-Constrained Crossbar Arrays00.342021
Diagnosis for Reconfigurable Single-Electron Transistor Arrays with a More Generalized Defect Model00.342021
Dynamic Workload Allocation for Edge Computing10.352021
A General Equivalence Checking Framework for Multivalued Logic00.342021
An Efficient Approximate Node Merging with an Error Rate Guarantee00.342021
1st-Order to 2nd-Order Threshold Logic Gate Transformation with an Enhanced ILP-based Identification Method00.342021
Rehabilitation System for Limbs using IMUs00.342020
IMU-based Smart Knee Pad for Walking Distance and Stride Count Measurement00.342020
A Dynamic Expansion Order Algorithm for the SAT-based Minimization00.342020
A New Necessary Condition for Threshold Function Identification00.342020
LOOPLock: Logic Optimization-Based Cyclic Logic Locking00.342020
Prediction of chronic kidney disease stages by renal ultrasound imaging00.342020
Accuracy Tolerant Neural Networks Under Aggressive Power Optimization.00.342020
Smartlock: Sat Attack And Removal Attack-Resistant Tree-Based Logic Locking00.342020
Optimization of Threshold Logic Networks with Node Merging and Wire Replacement.00.342019
Using range-equivalent circuits for facilitating bounded sequential equivalence checking00.342018
A Hybrid Approach to Equivalent Fault Identification for Verification Environment Qualification.00.342018
Contactless Testing for Prebond Interposers.00.342018
Efficient Synthesis Of Approximate Threshold Logic Circuits With An Error Rate Guarantee00.342018
On Synthesizing Memristor-Based Logic Circuits With Minimal Operational Pulses.20.442018
Enhancements to SAT Attack: Speedup and Breaking Cyclic Logic Encryption.00.342018
Optimization of threshold logic networks with ODC-based node merging00.342018
Logic Optimization With Considering Boolean Relations00.342018
Tree-Based Logic Encryption for Resisting SAT Attack00.342017
Dynamic Diagnosis for Defective Reconfigurable Single-Electron Transistor Arrays10.362017
Fast synthesis of threshold logic networks with optimization.30.462016
MSPlayer: Multi-Source and Multi-Path Video Streaming.70.522016
Minimization of Number of Neurons in Voronoi Diagram-Based Artificial Neural Networks.10.352016
Area-Aware Decomposition for Single-Electron Transistor Arrays.20.382016
Diagnosis and Synthesis for Defective Reconfigurable Single-Electron Transistor Arrays.30.392016
MajorSat: A SAT solver to majority logic00.342016
An Efficient Interpolation-Based Projected Sum of Product Decomposition via Genetic Algorithm.30.392016
Synthesis and verification of cyclic combinational circuits10.382015
Correctness Analysis and Power Optimization for Probabilistic Boolean Circuits10.372015
Using structural relations for checking combinationality of cyclic circuits10.372015
A defect-aware approach for mapping reconfigurable Single-Electron Transistor arrays30.402015
Synthesis for Width Minimization in the Single-Electron Transistor Array40.422015
Design, implementation, and evaluation of energy-aware multi-path TCP.140.602015
How green is multipath TCP for mobile devices?311.142014
Cross-layer path management in multi-path transport protocol for mobile devices210.942014
Rewiring for threshold logic circuit minimization20.402014
Improving Energy Efficiency of MPTCP for Mobile Devices.50.422014
Width minimization in the Single-Electron Transistor array synthesis60.552014
MSPlayer: Multi-Source and multi-Path LeverAged YoutubER.20.392014
Stage diagnosis for Chronic Kidney Disease based on ultrasonography00.342014
Multi-source multipath HTTP (mHTTP): a proposal70.612014
Hybrid LUT and SOP Reconfigurable Architecture.10.362014
On bufferbloat and delay analysis of multipath TCP in wireless networks40.562014
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