Name
Abstract | ||
|---|---|---|
This paper presents highly reliable reference bitline bias designs for 64 Mb and 128 Mb chain FeRAM™. The hysteresis shape deformation of ferroelectric capacitor due to temperature variation causes cell signal level shifts of both “1” and “0” data. The reference bitline bias of 64 Mb chip is designed to keep intermediate value of “1” and “0” data at any operating temperatures from C to 85 C by introducing a modified band-gap reference circuit with 3 bit temperature coefficient trimmers and 6 bit digital-to-analog converter (DAC) using laser fuses. The measured result shows the improvement of tail-to-tail cell signal windows by 22 mV. Moreover, a new reference bias circuit called the “elevator circuit” with 3 bit temperature coefficient trimmers using ferroelectric fuses installed in a 128 Mb chip compensates array operating voltage VAA fluctuation as well as temperature variation. The elevator circuit enables the temperature dependency control at low external VDD of 1.8 V. This improves cell signal window by 40 mV. The elevator circuit also varies reference bitline bias with array operating voltage VAA variation, resulting in improvement of cell signal windows by 44 mV in the range of 1.5 V 0.2 V VAA. |
Year | DOI | Venue |
|---|---|---|
2015 | 10.1109/JSSC.2015.2405932 | J. Solid-State Circuits |
Keywords | DocType | Volume |
ferroelectric capacitor,nonvolatile memory,reference voltage,feram,temperature,integrated circuit design,temperature measurement,hysteresis | Journal | 50 |
Issue | ISSN | Citations |
5 | 0018-9200 | 0 |
PageRank | References | Authors |
0.34 | 5 | 6 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Ryu Ogiwara | 1 | 32 | 5.33 |
| Daisaburo Takashima | 2 | 78 | 26.66 |
| Sumiko Doumae | 3 | 32 | 5.67 |
| Shinichiro Shiratake | 4 | 46 | 8.34 |
| Ryosuke Takizawa | 5 | 23 | 3.63 |
| Hidehiro Shiga | 6 | 41 | 15.51 |