Paper Info
Title
A 3.7 mW Low-Noise Wide-Bandwidth 4.5 GHz Digital Fractional-N PLL Using Time Amplifier-Based TDC
Abstract
A digital fractional-N PLL that employs a high resolution TDC and a truly ΔΣ fractional divider to achieve low in-band noise with a wide bandwidth is presented. The fractional divider employs a digital-to-time converter (DTC) to cancel out ΔΣ quantization noise in time domain, thus alleviating TDC dynamic range requirements. The proposed digital architecture adopts a narrow range low-power time-amplifier based TDC (TA-TDC) to achieve sub 1 ps resolution. By using TA-TDC in place of a BBPD, the limit cycle behavior that plagues BB-PLLs is greatly suppressed by the TA-TDC, thus permitting wide PLL bandwidth. The proposed architecture is also less susceptible to DTC nonlinearity and has faster settling and tracking behavior compared to a BB-PLL. Fabricated in 65 nm CMOS process, the prototype PLL achieves better than -106 dBc/Hz in-band noise and 3 MHz PLL bandwidth at 4.5 GHz output frequency using 50 MHz reference. The PLL consumes 3.7 mW and achieves better than 490 fsrms integrated jitter. This translates to a FoMJ of -240.5 dB, which is the best among the reported fractional-N PLLs.
Year
DOI
Venue
2015
10.1109/JSSC.2014.2385753
J. Solid-State Circuits
Keywords
Field
DocType
cmos integrated circuits,delta sigma modulation,phase locked loops,tdc,low power electronics,jitter,phase noise,bandwidth,frequency synthesizer
Phase-locked loop,Dynamic range,Control theory,Computer science,PLL multibit,Phase noise,Electronic engineering,Frequency synthesizer,Bandwidth (signal processing),Jitter,Amplifier
Journal
Volume
Issue
ISSN
50
4
0018-9200
Citations 
PageRank 
References 
27
1.39
21
Authors
5
Name
Order
Citations
PageRank
Ahmed Elkholy1333.01
Tejasvi Anand211016.98
Woo-Seok Choi310512.58
Amr Elshazly424228.08
Pavan Kumar Hanumolu555484.82