A 32 Gb/S Backplane Transceiver With On-Chip Ac-Coupling And Low Latency Cdr In 32 Nm Soi Cmos Technology - Citegraph

Paper Info

Title
A 32 Gb/S Backplane Transceiver With On-Chip Ac-Coupling And Low Latency Cdr In 32 Nm Soi Cmos Technology

Abstract
This paper describes key design features of a 32 Gb/s 4-tap FFE/15-tap DFE transceiver in 32 nm SOI CMOS which mitigate major sources of degradation in transceiver performance. The transceiver employs a passive feed-forward restore (FFR) scheme in an on-chip AC-coupling network to prevent pattern-dependent baseline wander, a low-latency clock and data recovery (CDR) to improve high-frequency jitter tolerance, and a token-based power management scheme to reduce supply ripple. At 32 Gb/s, the transceiver can equalize a channel with 30 dB of loss at a bit-error rate below 10(-12) while consuming 21 mW/Gbps at 1 V supply and an area of 0.7 mm(2).

Year	DOI	Venue
2014	10.1109/JSSC.2014.2340574	IEEE JOURNAL OF SOLID-STATE CIRCUITS
Keywords	Field	DocType
Low latency CDR, on-chip AC-coupling, serial links, token-based power management	Silicon on insulator,Power management,Transceiver,Backplane,Computer science,Communication channel,Real-time computing,Electronic engineering,Latency (engineering),Jitter,Capacitive coupling	Journal
Volume	Issue	ISSN
49	11	0018-9200
Citations	PageRank	References
7	1.28	9
Authors
19

Authors (19 rows)

Cited by (7 rows)

References (9 rows)

Name	Order	Citations	PageRank
Gautam R. Gangasani	1	25	4.18
Chun-Ming Hsu	2	37	6.00
John F. Bulzacchelli	3	281	42.62
Troy J. Beukema	4	287	69.47
william r kelly	5	25	3.51
Hui H. Xu	6	25	3.51
David Freitas	7	7	1.28
Andrea Prati	8	82	9.92
Daniele Gardellini	9	91	11.98
Robert Reutemann	10	57	7.69
Giovanni Cervelli	11	7	1.28
Juergen Hertle	12	64	8.39
Matthew Baecher	13	7	1.28
Jon Garlett	14	73	8.89
Pier Andrea Francese	15	138	25.33
John F. Ewen	16	7	1.28
David R. Hanson	17	431	107.79
Daniel Storaska	18	61	10.91
Mounir Meghelli	19	78	14.76

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