Name
Title | ||
|---|---|---|
340 mV–1.1 V, 289 Gbps/W, 2090-Gate NanoAES Hardware Accelerator With Area-Optimized Encrypt/Decrypt GF(2 4 ) 2 Polynomials in 22 nm Tri-Gate CMOS |
Abstract | ||
|---|---|---|
This paper describes an on-die lightweight nanoAES hardware accelerator, fabricated in 22 nm tri-gate high-k/metal-gate CMOS, targeted for ultra-low power symmetric-key encryption and decryption on mobile SOCs. Compared to conventional 128 bit AES implementations, this design uses a single 8 bit Sbox circuit along with ShiftRows byte-order data processing to compute all AES rounds in native GF(24)2 composite-field. This approach along with a serial-accumulating MixColumns circuit, area-optimized encrypt and decrypt Galois-field polynomials and integrated on-the-fly key generation circuit results in a compact encrypt/decrypt layout occupying 2200/2736 μm2 and lowest-reported gate count of 1947/2090 respectively, while achieving: (i) maximum operating frequency of 1.133 GHz and total power consumption of 13 mW with leakage component of 500 μW, measured at 0.9 V, 25 °C, (ii) nominal AES-128 encrypt/decrypt throughput of 432/671 Mbps respectively, with peak energy-efficiency of 289 Gbps/W measured at near-threshold operation of 430 mV (11 ×higher than previously reported implementations), (iii) encrypt/decrypt latencies of 336/216 cycles and total energy consumption of 3.9/2.5 nJ respectively, (iv) wide operating supply voltage range with robust sub-threshold voltage performance of 45 Mbps, 170 μW, measured at 340 mV, 25 °C and (v) first-reported Galois-field polynomial-based micro-architectural co-optimization, resulting in distinct area-optimized encrypt and decrypt polynomials with up to 9% area reduction at iso-performance. |
Year | DOI | Venue |
|---|---|---|
2015 | 10.1109/JSSC.2014.2384039 | J. Solid-State Circuits |
Keywords | Field | DocType |
encryption,security,polynomials,system on chip,hardware,registers,cmos integrated circuits,advanced encryption standard,throughput,cryptography,logic gates | Key generation,Gate count,Logic gate,Computer science,8-bit,CMOS,Electronic engineering,GF(2),AES implementations,128-bit | Journal |
Volume | Issue | ISSN |
50 | 4 | 0018-9200 |
Citations | PageRank | References |
18 | 0.94 | 7 |
Authors | ||
9 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Sanu Mathew | 1 | 50 | 3.78 |
| Sudhir Satpathy | 2 | 269 | 19.69 |
| Vikram Suresh | 3 | 19 | 3.00 |
| Mark Anders | 4 | 315 | 50.81 |
| Himanshu Kaul | 5 | 456 | 51.07 |
| Amit Agarwal | 6 | 693 | 72.95 |
| S. K. Hsu | 7 | 521 | 52.06 |
| Gregory K. Chen | 8 | 18 | 0.94 |
| Ram Krishnamurthy | 9 | 650 | 74.63 |