| Two-Round Maliciously Secure Computation with Super-Polynomial Simulation | 1 | 0.36 | 2021 |
| Self Adaptive Fruit Fly Algorithm For Multiple Workflow Scheduling In Cloud Computing Environment | 1 | 0.34 | 2021 |
| A 617-TOPS/W All-Digital Binary Neural Network Accelerator in 10-nm FinFET CMOS | 0 | 0.34 | 2021 |
| Toward Improving The Visual Characterization of Sport Activities With Abstracted Scene Graphs | 0 | 0.34 | 2021 |
| IRLCov19: A Large COVID-19 Multilingual Twitter Dataset of Indian Regional Languages | 0 | 0.34 | 2021 |
| Quantifying Health & Economic Benefits Of Bicycle Superhighway: Evidence From Patna | 0 | 0.34 | 2021 |
| Low-Clock-Power Digital Standard Cell IPs for High-Performance Graphics/AI Processors in 10nm CMOS | 0 | 0.34 | 2020 |
| An automated fault-tolerant route discovery with congestion control using TFRF model for 3D network-on-chips | 0 | 0.34 | 2020 |
| Performance Analysis Of Surrounding Cylindrical Gate All Around Nanowire Transistor For Biomedical Application | 0 | 0.34 | 2020 |
| A 4900- $\mu$ m 839-Mb/s Side-Channel Attack- Resistant AES-128 in 14-nm CMOS With Heterogeneous Sboxes, Linear Masked MixColumns, and Dual-Rail Key Addition. | 2 | 0.38 | 2020 |
| A Ray-Casting Accelerator in 10nm CMOS for Efficient 3D Scene Reconstruction in Edge Robotics and Augmented Reality Applications | 0 | 0.34 | 2020 |
| A 250Mv, 0.063J/Ghash Bitcoin Mining Engine in 14nm CMOS Featuring Dual-Vcc Sha256 Datapath and 3-Phase Latch Based Clocking | 0 | 0.34 | 2019 |
| A Microwatt-Class Always-On Sensor Fusion Engine Featuring Ultra-Low-Power AOI Clocked Circuits in 14nm CMOS | 1 | 0.37 | 2019 |
| A 220-900mV 179Mcode/s 36pJ/code Canonical Huffman Encoder for DEFLATE Compression in 14nm CMOS | 0 | 0.34 | 2019 |
| Can Twitter Help to Predict Outcome of 2019 Indian General Election - A Deep Learning Based Study. | 0 | 0.34 | 2019 |
| An All-Digital Unified Physically Unclonable Function and True Random Number Generator Featuring Self-Calibrating Hierarchical Von Neumann Extraction in 14-nm Tri-gate CMOS | 5 | 0.45 | 2019 |
| A 54% Power-Saving Static Fully-Interruptible Single-Phase-Clocked Shared-Keeper Flip-Flop in 14nm CMOS | 0 | 0.34 | 2019 |
| A 225-950mV 1.5Tbps/W Whirlpool Hashing Accelerator for Secure Automotive Platforms in 14nm CMOS | 0 | 0.34 | 2019 |
| A 1.4GHz 20.5Gbps GZIP decompression accelerator in 14nm CMOS featuring dual-path out-of-order speculative Huffman decoder and multi-write enabled register file array | 0 | 0.34 | 2019 |
| Ultra-Lightweight 548–1080 Gate 166Gbps/W–12.6Tbps/W SIMON 32/64 Cipher Accelerators for IoT in 14nm Tri-gate CMOS | 0 | 0.34 | 2018 |
| A 230mV-950mV 2.8Tbps/W Unified SHA256/SM3 Secure Hashing Hardware Accelerator in 14nm Tri-Gate CMOS. | 0 | 0.34 | 2018 |
| 34.4Mbps 1.56Tbps/W DEFLATE Decompression Accelerator Featuring Block-Adaptive Huffman Decoder in 14nm Tri-Gate CMOS for IoT Platforms. | 0 | 0.34 | 2018 |
| 2.9TOPS/W Reconfigurable Dense/Sparse Matrix-Multiply Accelerator with Unified INT8/INTI6/FP16 Datapath in 14NM Tri-Gate CMOS | 1 | 0.41 | 2018 |
| An All-Digital Unified Static/Dynamic Entropy Generator Featuring Self-Calibrating Hierarchical Von Neumann Extraction for Secure Privacy-Preserving Mutual Authentication in IoT Mote Platforms | 1 | 0.38 | 2018 |
| 220MV-900MV 794/584/754 GBPS/W Reconfigurable GF(2<sup>4</sup>)2 AES/SMS4/Camellia Symmetric-Key Cipher Accelerator in 14NM Tri-Gate CMOS | 0 | 0.34 | 2018 |
| A 280mV 3.1pJ/code Huffman Decoder for DEFLATE Decompression Featuring Opportunistic Code Skip and 3-way Symbol Generation in 14nm Tri-gate CMOS | 0 | 0.34 | 2018 |
| A Datamining Approach for Emotions Extraction and Discovering Cricketers performance from Stadium to Sensex. | 0 | 0.34 | 2018 |
| Passenger Abnormal Behaviour Detection using Machine Learning Approach | 0 | 0.34 | 2017 |
| A 305mV-850mV 400μW 45GSamples/J reconfigurable compressive sensing engine with early-termination for ultra-low energy target detection in 14nm tri-gate CMOS | 0 | 0.34 | 2016 |
| Implementing Cross-Device Atomics in Heterogeneous Processors | 1 | 0.35 | 2015 |
| Construction of a Semi-Automated model for FAQ Retrieval via Short Message Service. | 0 | 0.34 | 2015 |
| 340 mV–1.1 V, 289 Gbps/W, 2090-Gate NanoAES Hardware Accelerator With Area-Optimized Encrypt/Decrypt GF(2 4 ) 2 Polynomials in 22 nm Tri-Gate CMOS | 18 | 0.94 | 2015 |
| 13fJ/bit probing-resilient 250K PUF array with soft darkbit masking for 1.94% bit-error in 22nm tri-gate CMOS | 4 | 0.50 | 2014 |
| Efficient Optimal Algorithm of Task Scheduling in Cloud Computing Environment | 14 | 0.69 | 2014 |
| A 280 mV-to-1.1 V 256b Reconfigurable SIMD Vector Permutation Engine With 2-Dimensional Shuffle in 22 nm Tri-Gate CMOS | 4 | 0.61 | 2013 |
| A 2.05 GVertices/s 151 mW Lighting Accelerator for 3D Graphics Vertex and Pixel Shading in 32 nm CMOS. | 0 | 0.34 | 2013 |
| A 2.8GHz 128-entry × 152b 3-read/2-write multi-precision floating-point register file and shuffler in 32nm CMOS | 0 | 0.34 | 2012 |
| A 260mV 468GOPS/W 256b 4-way to 32-way vector shifter with permute-assisted skip in 22nm tri-gate CMOS | 0 | 0.34 | 2012 |
| A 1.45GHz 52-to-162GFLOPS/W variable-precision floating-point fused multiply-add unit with certainty tracking in 32nm CMOS. | 7 | 1.08 | 2012 |
| Near-threshold voltage (NTV) design: opportunities and challenges | 90 | 3.28 | 2012 |
| 2.4 Gbps, 7 mW All-Digital PVT-Variation Tolerant True Random Number Generator for 45 nm CMOS High-Performance Microprocessors | 31 | 2.05 | 2012 |
| A 128×128b high-speed wide-and match-line content addressable memory in 32nm CMOS | 9 | 0.72 | 2011 |
| A 4.1Tb/s bisection-bandwidth 560Gb/s/W streaming circuit-switched 8×8 mesh network-on-chip in 45nm CMOS | 1 | 0.35 | 2010 |
| A 320mV-to-1.2V on-die fine-grained reconfigurable fabric for DSP/media accelerators in 32nm CMOS | 18 | 1.85 | 2010 |
| A 300 Mv 494gops/W Reconfigurable Dual-Supply 4-Way Simd Vector Processing Accelerator In 45 Nm Cmos | 1 | 0.36 | 2010 |
| GSM based vehicle tracking system | 0 | 0.34 | 2010 |
| A 320 Mv 56 Mu W 411 Gops/Watt Ultra-Low Voltage Motion Estimation Accelerator In 65 Nm Cmos | 19 | 2.98 | 2009 |
| Within-Die Variation-Aware Scheduling in Superscalar Processors for Improved Throughput | 11 | 0.75 | 2008 |
| A 320mV 56μW 411GOPS/Watt Ultra-Low Voltage Motion Estimation Accelerator in 65nm CMOS. | 32 | 7.55 | 2008 |
| Device-aware yield-centric dual-Vt design under parameter variations in nanoscale technologies | 6 | 0.49 | 2007 |
