Name
Title | ||
|---|---|---|
Hardware architecture of bi-cubic convolution interpolation for real-time image scaling |
Abstract | ||
|---|---|---|
This paper presents two hardware architectures of bi-cubic convolution interpolation termed Parallelized Row Column Interpolation Architecture (PRCIA) and Serialized Row Column Interpolation Architecture (SRCIA) for real-time image scaling. These architectures factor in the challenges of high computational complexity, redundant computations and repeated memory accesses, which were otherwise not explicitly addressed in existing architectures. Besides, the proposed architectures also employ parallel computations to improve the throughput for realtime applications. The proposed architectures have been emulated and tested on Virtex-6 FPGA. The emulated PRCIA and SRCIA are able to scale input grayscale images of dimensions up to 640 × 480 at 59 and 48 frames per second respectively with arbitrary scaling factors up to 4 in both dimensions. |
Year | DOI | Venue |
|---|---|---|
2014 | 10.1109/FPT.2014.7082790 | Field-Programmable Technology |
Keywords | Field | DocType |
convolution,field programmable gate arrays,image processing,interpolation,PRCIA,SRCIA,Virtex-6 FPGA,bicubic convolution interpolation,grayscale images,hardware architecture,parallel computations,parallelized row column interpolation architecture,real-time image scaling,serialized row column interpolation architecture | Row and column spaces,Computer science,Convolution,Interpolation,Parallel computing,Field-programmable gate array,Frame rate,Image scaling,Grayscale,Hardware architecture | Conference |
ISBN | Citations | PageRank |
978-1-4799-6244-0 | 0 | 0.34 |
References | Authors | |
9 | 5 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Gopinath Mahale | 1 | 3 | 1.74 |
| Hamsika Mahale | 2 | 4 | 1.10 |
| Rajesh Babu Parimi | 3 | 0 | 0.34 |
| Nandy, S.K. | 4 | 43 | 7.29 |
| S. Bhattacharya | 5 | 0 | 0.34 |