Name
Abstract | ||
|---|---|---|
Sparse Matrix-Vector Multiplication (SpMxV) algorithms suffer heavy performance penalties due to irregular memory accesses. In this paper, we introduce a novel compressed element storage (CES) format, in which the additional data structures for indexing are abandoned, and each location associated with the non-zero element of the matrix is now indicated by the name of a variable multiplied by the corresponding element of the vector. To ensure fastest access and parallel access without data hazards, on-chip registers are used exclusively to replace the BRAM or off-chip DRAM/SRAM to hold all the SpMxV data. On-chip DSP resources are fully utilized so as to ensure a maximum number of multipliers concurrently working. |
Year | DOI | Venue |
|---|---|---|
2014 | 10.1109/FPT.2014.7082800 | FPT |
Keywords | Field | DocType |
matrix multiplication,spmxv data algorithm,sparse matrices,no zero padded,additional data structures,data structures,data hazards,heavy performance penalty,on-chip dsp resources,parallel access,indexing,digital signal processing chips,compressed element storage format,zero padded element,fpga,irregular memory accesses,off-chip dram-sram,ces format,sparse matrix-vector multiplication,field programmable gate arrays,on-chip registers,smvm,bram | Dram,Data structure,Matrix (mathematics),Computer science,Sparse matrix-vector multiplication,Parallel computing,Search engine indexing,Field-programmable gate array,Static random-access memory,Multiplication | Conference |
Citations | PageRank | References |
0 | 0.34 | 7 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jia-Sen Huang | 1 | 11 | 2.22 |
| Junyan Ren | 2 | 154 | 41.40 |
| Wenbo Yin | 3 | 5 | 1.75 |
| Lingli Wang | 4 | 86 | 25.42 |