Name
Abstract | ||
|---|---|---|
A novel differential dynamic CMOS logic using multiple-input floating-gate MOS(FGMOS) transistors is proposed. In this circuit family, a pair of n-channel multiple-input FGMOS pull down logic networks is used to replace the nMOS logic tree in the conventional dynamic differential cascode voltage switch logic circuit. A simple synthesis technique of the n-channel multiple-input FGMOS logic tree by employing summation signal is also discussed. By using multiple-input FGMOS, the logic tree can be significantly simplified. HSPICE simulations using TSMC 0.35μm 2-ploy 4-metal CMOS technology have verified the effectiveness of the proposed design scheme. |
Year | DOI | Venue |
|---|---|---|
2013 | 10.1109/ASICON.2013.6811997 | ASICON |
Keywords | Field | DocType |
floating gate mos transistors,nmos logic tree,fgmos logic tree,hspice simulations,2-ploy 4-metal cmos technology,size 0.35 mum,clocks,cmos logic circuits,logic design,fgmos pull down logic networks,clocked differential switch logic,dynamic differential cascode voltage switch logic circuit,mosfet,differential dynamic cmos logic | Logic gate,NMOS logic,Pass transistor logic,AND-OR-Invert,Computer science,Logic optimization,Electronic engineering,Resistor–transistor logic,Logic level,Logic family,Electrical engineering | Conference |
ISSN | ISBN | Citations |
2162-7541 | 978-1-4673-6415-7 | 2 |
PageRank | References | Authors |
0.45 | 2 | 5 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Guoqiang Hang | 1 | 7 | 5.83 |
| Yang Yang | 2 | 181 | 30.09 |
| Peiyi Zhao | 3 | 96 | 9.81 |
| Xiaohui Hu | 4 | 7 | 2.27 |
| xiaohu you | 5 | 2529 | 272.49 |