Name
Abstract | ||
|---|---|---|
The exponential advance in semiconductor manufacturing technology is bringing heavy increase not only in power consumption but in test data volume as well. Moreover, power consumption in test mode is much higher than that in the functional operation mode. In this paper, a low power scan bypass technique is proposed to reduce both the test data volume and the test power consumption. The proposed technique can reduce both test data volume and power consumption with the minimal impact on area overhead. Unused segments, which consist of don't care bits, can be bypassed in the proposed scan bypass technique. In order to maximize the bypassing portion, scan cell ordering and pattern ordering are performed. Experimental results show that the proposed technique efficiently reduce test power and test data volume with a small overhead. |
Year | DOI | Venue |
|---|---|---|
2015 | 10.1109/ISQED.2015.7085419 | ISQED |
Keywords | Field | DocType |
logic gates,low power electronics,vlsi,power dissipation,very large scale integration,benchmark testing | Automatic test pattern generation,Logic gate,Computer science,Dissipation,Semiconductor device fabrication,Electronic engineering,Real-time computing,Test data,Test compression,Very-large-scale integration,Benchmark (computing) | Conference |
ISSN | Citations | PageRank |
1948-3287 | 1 | 0.36 |
References | Authors | |
9 | 5 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Hyunyul Lim | 1 | 20 | 4.46 |
| Wooheon Kang | 2 | 22 | 3.46 |
| Sungyoul Seo | 3 | 10 | 3.27 |
| Yong Lee | 4 | 1 | 0.36 |
| Sungho Kang | 5 | 436 | 78.44 |